Johannes Kutning 0d1b73e3e0 Initial commit
2023-10-31 07:47:27 +01:00

10 lines
208 B
VHDL

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.test_utility.all;
package crc_data is
constant expected : std_logic_vector( 31 downto 0 ) := x"4d540e72";
end package crc_data;