218 lines
7.9 KiB
VHDL
218 lines
7.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.avalon_slave.all;
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use work.test_utility.all;
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use work.test_avalon_slave.all;
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use work.task.all;
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package test_hardware_task is
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procedure read_state( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable state : out std_logic_vector );
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procedure assert_state_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable state : std_logic_vector );
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procedure assert_cycle_count_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable cycle_count : std_logic_vector );
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procedure write_start( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request );
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procedure write_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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variable index : in integer;
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variable config : in std_logic_vector );
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procedure assert_config_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable index : in integer;
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variable config : in std_logic_vector );
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procedure write_and_assert_config_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable index : in integer;
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variable config : in std_logic_vector );
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procedure assert_output_steam_data_eq( signal clk : in std_logic;
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signal write : std_logic;
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signal writedata : std_logic_vector;
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signal expected : work.reg32.RegArray );
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procedure test_execute( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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signal write : in std_logic;
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signal writedata : in std_logic_vector );
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end package test_hardware_task;
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package body test_hardware_task is
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procedure read_state( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable state : out std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 1, address'length ) );
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work.test_avalon_slave.read( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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data => state );
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end procedure read_state;
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procedure assert_state_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable state : std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 1, address'length ) );
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => state,
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message => TEST_FAIL & " assert_state_eq" );
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end procedure assert_state_eq;
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procedure assert_cycle_count_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable cycle_count : std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 2, address'length ) );
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => cycle_count,
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message => TEST_FAIL & " assert_cycle_count_eq" );
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end procedure assert_cycle_count_eq;
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procedure write_start( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request ) is
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variable address : std_logic_vector( 3 downto 0 );
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variable start : std_logic_vector( 31 downto 0 ) := ( others => '0' );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 0, address'length ) );
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work.test_avalon_slave.write( clk => clk,
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address => address,
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req => req,
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data => START );
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end procedure write_start;
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procedure write_config( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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variable index : in integer;
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variable config : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 3 + index, address'length ) );
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work.test_avalon_slave.write( clk => clk,
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address => address,
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req => req,
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data => config );
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end procedure write_config;
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procedure assert_config_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable index : in integer;
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variable config : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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wait until falling_edge( clk );
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address := std_logic_vector( to_unsigned( 3 + index, address'length ) );
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work.test_avalon_slave.assert_readdata_eq( clk => clk,
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address => address,
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req => req,
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rsp => rsp,
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expected => config,
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message => TEST_FAIL & " assert_config_eq" );
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end procedure assert_config_eq;
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procedure write_and_assert_config_eq( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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variable index : in integer;
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variable config : in std_logic_vector ) is
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variable address : std_logic_vector( 3 downto 0 );
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begin
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write_config( clk => clk, req => req, index => index, config => config );
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assert_config_eq( clk => clk, req => req, rsp => rsp, index => index, config => config );
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end procedure write_and_assert_config_eq;
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procedure assert_output_steam_data_eq( signal clk : in std_logic;
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signal write : std_logic;
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signal writedata : std_logic_vector;
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signal expected : work.reg32.RegArray ) is
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begin
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end procedure assert_output_steam_data_eq;
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procedure test_execute( signal clk : in std_logic;
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signal req : out work.avalon_slave.Request;
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signal rsp : in work.avalon_slave.Response;
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signal write : in std_logic;
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signal writedata : in std_logic_vector ) is
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variable expected_readdata : std_logic_vector( 31 downto 0 );
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variable state : std_logic_vector( 31 downto 0 );
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variable index : integer := 0;
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begin
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std.textio.write( std.textio.OUTPUT, " test_execute ... " );
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expected_readdata := to_std_logic_vector( TASK_IDLE, expected_readdata'length );
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assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );
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write_start( clk => clk, req => req );
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expected_readdata := to_std_logic_vector( TASK_RUNNING, expected_readdata'length );
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assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );
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while true loop
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work.test_hardware_task.read_state( clk => clk, req => req, rsp => rsp, state => state );
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if ( state = to_std_logic_vector( TASK_DONE, expected_readdata'length ) ) then
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exit;
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end if;
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end loop;
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std.textio.write( std.textio.OUTPUT, TEST_OK );
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end procedure test_execute;
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end package body test_hardware_task;
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