signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

    signal float_add_start : std_logic := '0';
    signal float_add_done : std_logic;
    signal float_add_a : std_logic_vector(31 downto 0);
    signal float_add_b : std_logic_vector(31 downto 0);
    signal float_add_sum : std_logic_vector(31 downto 0) := (others => '0');

	type CalcState is (
		CALC_IDLE,
		CALC_ADD,
		CALC_STORE_RESULT
	);
	signal current_calc_state : CalcState;
	signal next_calc_state : CalcState;


	begin

    u_float_add : entity work.float_add
	port map(
	    clk => clk,
	    reset => reset,
	    start => float_add_start,
	    done => float_add_done,
	    A => float_add_a,
	    B => float_add_b,
	    sum => float_add_sum
    );


    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;


	calc_state_transistions : process (current_calc_state, current_task_state, float_add_done) is
	begin
		next_calc_state <= current_calc_state;
		case current_calc_state is
			when CALC_IDLE =>
				if current_task_state = work.task.TASK_RUNNING then
					next_calc_state <= CALC_ADD;
				end if;
			when CALC_ADD =>
				if (float_add_done = '1') then
					next_calc_state <= CALC_STORE_RESULT;
				end if;
			when CALC_STORE_RESULT => 
				next_calc_state <= CALC_IDLE;
		end case;
	end process calc_state_transistions;


-- Synchronisation: Task-State
    task_sync : process (clk, reset) is
    begin
        if (reset = '1') then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
            signal_write <= '0';
            signal_writedata <= (others => '0');
        elsif (rising_edge(clk)) then
            current_task_state <= next_task_state;

            if current_task_state = work.task.TASK_RUNNING then		
                -- Vorbereitung auf neue Berechnung
                if index > 0 then
					signal_a_read <= '1';
                	signal_b_read <= '1';
				end if;--index <= index + 1;
            else
                signal_a_read <= '0';
                signal_b_read <= '0';
				--index <= 0;
            end if;

            if current_calc_state = CALC_STORE_RESULT then
				signal_a_read <= '0';
				signal_b_read <= '0';
                signal_write <= '1';
                signal_writedata <= float_add_sum;
                index <= index + 1;
            else
                signal_write <= '0';
            end if;
        end if;
    end process task_sync;

    -- Synchronisation: Calc-State
    calc_sync : process (clk, reset) is
    begin
        if (reset = '1') then
            current_calc_state <= CALC_IDLE;
            float_add_start <= '0';
            float_add_a <= (others => '0');
            float_add_b <= (others => '0');
        elsif (rising_edge(clk)) then
            current_calc_state <= next_calc_state;

            case current_calc_state is
                when CALC_IDLE =>
                    float_add_start <= '0';
                when CALC_ADD =>
                    float_add_a <= signal_a_readdata;
                    float_add_b <= signal_b_readdata;
                    float_add_start <= '1';
                when CALC_STORE_RESULT =>
                    float_add_start <= '0';
            end case;
        end if;
    end process calc_sync;

    task_state <= current_task_state;


end architecture rtl;