115 lines
3.5 KiB
VHDL
115 lines
3.5 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
library work;
|
|
use work.reg32.all;
|
|
use work.task.all;
|
|
|
|
entity rand is
|
|
port (
|
|
clk : in std_logic;
|
|
reset : in std_logic;
|
|
|
|
task_start : in std_logic;
|
|
task_state : out work.task.State;
|
|
seed : in work.reg32.word;
|
|
|
|
signal_write : out std_logic;
|
|
signal_writedata : out std_logic_vector(31 downto 0)
|
|
);
|
|
end entity rand;
|
|
|
|
architecture rtl of rand is
|
|
signal lfsr_reg : std_logic_vector(31 downto 0);
|
|
signal current_task_state : work.task.State;
|
|
signal next_task_state : work.task.State;
|
|
signal index : integer range 0 to work.task.STREAM_LEN;
|
|
|
|
begin
|
|
|
|
task_state_transitions : process(current_task_state, task_start, index) is
|
|
begin
|
|
next_task_state <= current_task_state;
|
|
case current_task_state is
|
|
when work.task.TASK_IDLE =>
|
|
if (task_start = '1') then
|
|
next_task_state <= work.task.TASK_RUNNING;
|
|
end if;
|
|
when work.task.TASK_RUNNING =>
|
|
if (index = work.task.STREAM_LEN - 1) then
|
|
next_task_state <= work.task.TASK_DONE;
|
|
end if;
|
|
when work.task.TASK_DONE =>
|
|
if (task_start = '1') then
|
|
next_task_state <= work.task.TASK_RUNNING;
|
|
end if;
|
|
end case;
|
|
end process task_state_transitions;
|
|
|
|
|
|
sync : process(clk, reset) is
|
|
variable random_value : std_logic_vector(31 downto 0);
|
|
variable lfsr_feedback : std_logic;
|
|
begin
|
|
if (reset = '1') then
|
|
current_task_state <= work.task.TASK_IDLE;
|
|
index <= 0;
|
|
lfsr_reg <= seed;
|
|
signal_write <= '0';
|
|
elsif (rising_edge(clk)) then
|
|
|
|
lfsr_feedback := lfsr_reg(31) xor lfsr_reg(21) xor lfsr_reg(1) xor lfsr_reg(0);
|
|
--lfsr_reg <= lfsr_feedback & lfsr_reg(31 downto 1);
|
|
|
|
current_task_state <= next_task_state;
|
|
|
|
case next_task_state is
|
|
when work.task.TASK_IDLE =>
|
|
index <= 0;
|
|
signal_write <= '0';
|
|
lfsr_reg <= seed;
|
|
|
|
when work.task.TASK_RUNNING =>
|
|
|
|
lfsr_reg <= lfsr_feedback & lfsr_reg(31 downto 1);
|
|
random_value := lfsr_reg;
|
|
|
|
|
|
if random_value(30) = '1' then
|
|
|
|
random_value(29 downto 24) := "000000"; -- Exponent 129 (2^3)
|
|
--random_value(6 downto 1) := (others => '0');
|
|
random_value(23) := lfsr_reg(7);
|
|
end if;
|
|
if random_value(30) = '0' then
|
|
|
|
random_value(29 downto 25) := "11111"; -- Exponent 123 (2^-3)
|
|
--random_value(6 downto 2) := (others => '1');
|
|
random_value(24 downto 23) := lfsr_reg(5 downto 4);
|
|
end if;
|
|
|
|
|
|
random_value(31) := lfsr_reg(14);
|
|
|
|
|
|
signal_write <= '1';
|
|
signal_writedata <= random_value;
|
|
|
|
|
|
--lfsr_reg <= lfsr_feedback & lfsr_reg(31 downto 1);
|
|
|
|
|
|
index <= index + 1;
|
|
|
|
when work.task.TASK_DONE =>
|
|
index <= 0;
|
|
signal_write <= '0';
|
|
end case;
|
|
end if;
|
|
end process sync;
|
|
|
|
task_state <= current_task_state;
|
|
|
|
end architecture rtl;
|