brandlfl78731 c9ca4d965a Versuch 3 Hardware funktioniert Juhu!

2024-12-18 09:18:47 +01:00

hardware

Versuch 3 Hardware funktioniert Juhu!

2024-12-18 09:18:47 +01:00

software

Versuch 3 CRC, Software fertig

2024-12-04 11:19:36 +01:00

tests

Versuch 3 Hardware funktioniert Juhu!

2024-12-18 09:18:47 +01:00

.gitignore

Initial commit

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data_channel_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_task_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_timestamp_hw.tcl

Initial commit

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hdl_sources.qsf

Initial commit

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init.sh

Initial commit

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Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qpf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

Description

Studentenversion des ESY6/A Praktikums "signal_processing".

19 MiB

Languages

VHDL 37.3%

C 17.2%

Verilog 15%

Python 10.7%

Makefile 8.2%

Other 11.6%