233 lines
6.6 KiB
VHDL
233 lines
6.6 KiB
VHDL
------------------------------------------------------------------------
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-- fft
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--
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-- calculation of FFT magnitude
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--
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-- Inputs:
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-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
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--
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-- Outputs
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-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
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--
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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use work.float.all;
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entity fft is
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generic (
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity fft;
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architecture rtl of fft is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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component fftmain is
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-- generic( width : integer := 32
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--);
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port(
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clock: in std_logic;
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reset: in std_logic;
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di_en: in std_logic;
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di_re: in std_logic_vector(input_data_width-1 downto 0);
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di_im: in std_logic_vector(input_data_width-1 downto 0);
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do_en: out std_logic;
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do_re: out std_logic_vector(output_data_width-1 downto 0);
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do_im: out std_logic_vector(output_data_width-1 downto 0)
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);
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end component;
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-- Zustände für die Zustandsmaschine zur Berechnung
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type SigState is (
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SIG_IDLE,
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SIG_READ,
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SIG_FFTMAIN,
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SIG_FFTMAG,
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SIG_WRITE
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);
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signal current_sig_state : SigState;
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signal next_sig_state : SigState;
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signal fftmain_start : std_logic;
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signal fftmain_done : std_logic;
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signal fftmag_start : std_logic;
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signal fftmag_done : std_logic;
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signal fftmain_out_re : std_logic_vector( 31 downto 0 );
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signal fftmain_out_im : std_logic_vector( 31 downto 0 );
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signal exp : std_logic_vector( 7 downto 0);
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signal scaled_exp : std_logic_vector( 7 downto 0);
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signal scaled_readdata : std_logic_vector( 31 downto 0);
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signal exp_int : integer;
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signal scaled_data_fixp : std_logic_vector(31 downto 0);
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signal exp2 : std_logic_vector( 7 downto 0);
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signal scaled_exp2 : std_logic_vector( 7 downto 0);
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signal exp_int2 : integer;
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signal magnitude_output : std_logic_vector( 31 downto 0 );
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signal writedata_float : std_logic_vector( 31 downto 0 );
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type std_logic_vector_array is array (0 to 1023) of std_logic_vector(31 downto 0);
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signal my_array : std_logic_vector_array;
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begin
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exp <= signal_readdata( 30 downto 23 );
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exp_int <= to_integer(unsigned(exp));
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scaled_exp <= std_logic_vector(to_unsigned(exp_int - 4, 8));
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scaled_readdata <= signal_readdata( 31 ) & scaled_exp & signal_readdata( 22 downto 0 );
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scaled_data_fixp <= to_fixed(scaled_readdata);
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writedata_float <= to_float(magnitude_output);
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exp2 <= writedata_float( 30 downto 23 );
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exp_int2 <= to_integer(unsigned(exp2));
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scaled_exp2 <= std_logic_vector(to_unsigned(exp_int2 + 5, 8));
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my_array(1023 - index) <= writedata_float( 31 ) & scaled_exp2 & writedata_float( 22 downto 0 );
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signal_writedata <= my_array(index);
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u_fft : fftmain
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port map (
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clock => clk,
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reset => reset,
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di_en => fftmain_start,
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di_re => scaled_data_fixp,
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di_im => x"00000000",
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do_en => fftmain_done,
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do_re => fftmain_out_re,
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do_im => fftmain_out_im
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);
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u_fft_mag_calc : entity work.fft_magnitude_calc
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port map (
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clk => clk,
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reset => reset,
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input_valid => fftmag_start,
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input_re => fftmain_out_re,
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input_im => fftmain_out_im,
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output_valid => fftmag_done,
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output_magnitude => magnitude_output
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);
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sig_state_transitions : process (all) is
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begin
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next_sig_state <= current_sig_state;
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case current_sig_state is
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when SIG_IDLE =>
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if ( current_task_state = work.task.TASK_RUNNING ) then
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next_sig_state <= SIG_READ;
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end if;
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when SIG_READ =>
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next_sig_state <= SIG_FFTMAIN;
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when SIG_FFTMAIN =>
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if ( fftmain_done = '1') then
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next_sig_state <= SIG_FFTMAG;
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end if;
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when SIG_FFTMAG =>
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if ( fftmain_done = '0') then
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next_sig_state <= SIG_WRITE;
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end if;
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when SIG_WRITE =>
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null;
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end case;
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end process sig_state_transitions;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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current_sig_state <= SIG_IDLE;
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index <= 0;
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signal_read <= '0';
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fftmain_start <= '0';
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fftmag_start <= '0';
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signal_write <= '0';
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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null;
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when work.task.TASK_RUNNING =>
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null;
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when work.task.TASK_DONE =>
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null;
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end case;
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current_sig_state <= next_sig_state;
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case next_sig_state is
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when SIG_IDLE =>
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signal_write <= '0';
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when SIG_READ =>
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signal_read <= '1';
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when SIG_FFTMAIN =>
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fftmain_start <= '1';
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when SIG_FFTMAG =>
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signal_read <= '0';
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fftmain_start <= '0';
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fftmag_start <= '1';
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signal_write <= '0';
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index <= index + 1;
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when SIG_WRITE =>
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fftmag_start <= '0';
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signal_write <= '1';
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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