Adds U4 FSM
This commit is contained in:
parent
4e8daa20bd
commit
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vhdl_srcs = down_counter_int.vhd \
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vhdl_srcs = ../scripts/test_utility.vhd \
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top_entity.vhd \
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squareRoot_pipe.vhd \
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test_top_entity.vhd \
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fft_magnitude_calc.vhd \
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test_fsm.vhd \
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main = test_top_entity
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main = tb_fft_magnitude_calc
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CHECK_RESULTS = true
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CHECK_RESULTS = true
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BIN
U4_FSM/Zustandsmaschine.pdf
Normal file
BIN
U4_FSM/Zustandsmaschine.pdf
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Binary file not shown.
153
U4_FSM/fft_magnitude_calc.vhd
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U4_FSM/fft_magnitude_calc.vhd
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------------------------------------------------------------------------
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-- fft_magnitude_calc
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--
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-- calculation of FFT magnitude sqrt(real_part²+im_part²)
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-- Inputs:
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-- input_re in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
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-- input_im in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
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-- input_valid: high = inputs are valid for data processing
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-- Outputs
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-- output_magnitude: Fixpoint 0.5=0x40000000 (always positive)
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-- output_valid: high = magnitude data is valid
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fft_magnitude_calc is
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port (
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clk : in std_logic; -- Takt
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reset : in std_logic; -- Reset
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input_valid: in std_logic; -- Eingangsdaten gueltig
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input_re : in std_logic_vector( 31 downto 0 ); -- Realteil in Fixpoint
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input_im : in std_logic_vector( 31 downto 0 ); -- Imaginaerteil in Fixpoint
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output_valid : out std_logic; -- Ausgangsdaten gueltig
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output_magnitude : out std_logic_vector( 31 downto 0 ) -- Berechnete magnitude
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);
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end entity fft_magnitude_calc;
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architecture rtl of fft_magnitude_calc is
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-- Zustaende fuer die Zustandsmaschine fuer die Berechnung
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type CalcState is (
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CALC_IDLE, -- Zustand Leerlauf
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CALC_MULTIPLY, -- Zustand Berechnung real_part² und im_part²
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CALC_ADD, -- Zustand Berecnung Addition real_part²+im_part²
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CALC_SQRT, -- Zustand Berechnung der sqrt(real_part²+im_part²)
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CALC_STORE_RESULT -- Zustand Setzen von output_valid und output_magnitude
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);
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-- Legen Sie die Signale current_calc_state und next_calc_state fuer die Zustandsmaschine CalcState an
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-- Legen Sie die Signale re_multiply_re und im_multiply_im als signed (63 downto 0) an
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-- Legen Sie die Signal re2_add_im2 als signed (63 downto 0) an
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-- Legen Sie die Signal output_sqrt als std_logic_vector (31 downto 0) an
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-- Legen Sie die Signal output_sqrt als std_logic_vector (15 downto 0) an
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-- Legen Sie das Signal start_sqrt_calc als std_logic an
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-- Legen Sie das Signal sqrt_out_valid_flag als std_logic an
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begin
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-- uebergangsschaltnetz der Zustandsmaschine fuer die Berechnung (Strukturvariante 2 Process Zustandsmaschine)
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-- Beschreiben Sie den Prozess fuer das uebergangsschaltnetz (Case-Anweisung)
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-- CALC_IDLE -> CALC_MULTIPLY wenn input_valid = 1
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-- CALC_MULTIPLY -> CALC_ADD
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-- CALC_ADD -> CALC_SQRT
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-- CALC_SQRT -> CALC_STORE_RESULT wenn sqrt_out_valid_flag = 1
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-- CALC_STORE_RESULT -> CALC_IDLE
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calc_state_transitions : process ( all ) is
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begin
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end process calc_state_transitions;
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-- Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Berechnung (Strukturvariante 2 Process Zustandsmaschine)
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sync : process ( clk, reset ) is
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begin
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-- Der Prozess steuert folgende Signale setzen Sie fuer alle passende Resetwerte
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-- current_calc_state
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-- re_multiply_re
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-- im_multiply_im
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-- re2_add_im2
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-- input_sqrt
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-- start_sqrt_calc
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-- output_valid
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-- output_magnitude
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if ( reset = '1' ) then
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elsif ( rising_edge( clk ) ) then
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-- Machen Sie Anweisungen um start_sqrt_calc und output_valid auf 0 zu setzen
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-- Realisieren Sie den Zustandsspeicher current_calc_state
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-- Vervollstaendigen Sie das Ausgangsschaltnetz
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case next_calc_state is
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when CALC_IDLE=> null;
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-- calculation of real_part² and im_part²
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-- Anweisung fuer die Berechnung von re_multiply_re = input_re² (Datentypen beachten)
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-- Anweisung fuer die Berechnung von im_multiply_im = input_im² (Datentypen beachten)
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when CALC_MULTIPLY =>
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-- calculation of real_part²*+im_part²
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-- Anweisung fuer die Berechnung von re2_add_im2 = re_multiply_re + im_multiply_im
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when CALC_ADD =>
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-- calculation of sqrt(real_part²+im_part²)
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-- Anweisung um input_sqrt mit den obersten 32-Bit von re2_add_im2 zu belegen (Datentypen beachten)
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-- Anweisung um start_sqrt_calc mit 1 zu setzen
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when CALC_SQRT =>
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-- Setzen der Entity-Ausgaenge
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-- Anweisung um die obersten 16 bit von output_magnitude mit output_sqrt zu setzen und die untern 16 Bit mit 0
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-- Anweisung um output_valid mit 1 zu setzen
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when CALC_STORE_RESULT =>
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when others => NUll;
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end case;
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end if;
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end process sync;
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-- Instanziierung des SQRT Moduls fuer die Berechnung der Quardratwurzel
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-- Weisen Sie die Signale output_sqrt, reset, input_sqrt und clk richtig zu
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sqrt_module : entity work.squareRoot_pipe
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generic map (
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G_DATA_W => 32
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)
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port map (
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clk => ,
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rst => ,
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iv_data => ,
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ov_res =>
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);
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-- Dieser Prozess sorgt dafuer, dass 16 Takte nachdem start_sqrt_calc 1 geworden ist sqrt_out_valid_flag zu 1 wird
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-- Wird benoetigt um die Berechnungsdauer des sqrt_module anzueigen
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-- Hier muss nichts veraendert werden
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p_sqrt_out_valid_flag: process ( clk, reset ) is
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variable delay_sqrt_out_valid_flag : std_logic_vector(14 downto 0);
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begin
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if ( reset = '1' ) then
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sqrt_out_valid_flag <= '0';
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delay_sqrt_out_valid_flag := (others => '0');
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elsif ( rising_edge( clk ) ) then
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sqrt_out_valid_flag <= delay_sqrt_out_valid_flag(14);
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delay_sqrt_out_valid_flag := delay_sqrt_out_valid_flag(13 downto 0) & start_sqrt_calc;
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if sqrt_out_valid_flag = '1' then
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delay_sqrt_out_valid_flag := (others => '0');
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end if;
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end if;
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end process p_sqrt_out_valid_flag;
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end architecture rtl;
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U4_FSM/squareRoot_pipe.vhd
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U4_FSM/squareRoot_pipe.vhd
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----------------------------------------------------------------------------------------------------
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-- Component : squareRoot_pipe
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-- Author : pwkolas
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----------------------------------------------------------------------------------------------------
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-- File : squareRoot_pipe.vhd
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-- Mod. Date : XX.XX.XXXX
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-- Version : 1.00
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----------------------------------------------------------------------------------------------------
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-- Description : Square root calculator.
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-- Based on
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-- "A New Non-Restoring Square Root Algorithm and Its VLSI Implementations"
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--
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----------------------------------------------------------------------------------------------------
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-- Modification History :
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--
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----------------------------------------------------------------------------------------------------
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-- Comments :
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--
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----------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity squareRoot_pipe is
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generic (
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G_DATA_W : integer := 32
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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iv_data : in std_logic_vector(G_DATA_W-1 downto 0);
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ov_res : out std_logic_vector((G_DATA_W/2)-1 downto 0)
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);
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end entity squareRoot_pipe;
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architecture squareRoot_pipe_rtl of squareRoot_pipe is
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constant C_ALU_W : integer := ((G_DATA_W/2) + 2);
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constant C_PIPE_L : integer := G_DATA_W/2;
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constant C_OFFSET : integer := 3; -- width of start vectors going to ALU
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type t_arr_pipe_x_data is array (C_PIPE_L-1 downto 0) of unsigned(G_DATA_W-1 downto 0);
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signal a_data : t_arr_pipe_x_data; -- (D)
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signal a_R : t_arr_pipe_x_data; -- (R)
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type t_arr_pipe_x_alu is array (C_PIPE_L-1 downto 0) of unsigned(C_ALU_W-1 downto 0);
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type t_arr_pipe_x_res is array (C_PIPE_L-1 downto 0) of unsigned(G_DATA_W/2-1 downto 0);
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signal a_Q : t_arr_pipe_x_res; -- (ALU Q out)
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signal nextOp : std_logic_vector(C_PIPE_L-1 downto 0);
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begin
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sqrt_p : process (clk, rst)
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variable va_AluInR : t_arr_pipe_x_alu; -- (ALU R in)
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variable va_AluInQ : t_arr_pipe_x_alu; -- (ALU Q in)
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variable va_AluOut : t_arr_pipe_x_alu; -- (ALU Q out)
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begin
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if (rst = '1') then
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a_data <= (others => (others => '0'));
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a_R <= (others => (others => '0'));
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a_Q <= (others => (others => '0'));
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va_AluInR := (others => (others => '0'));
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va_AluInQ := (others => (others => '0'));
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va_AluOut := (others => (others => '0'));
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nextOp <= (others => '0');
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elsif rising_edge(clk) then
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-- stage 0 start conditions, ALU inputs
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va_AluInR(0) := (others => '0');
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va_AluInR(0)(1 downto 0) := unsigned(iv_data(G_DATA_W-1 downto G_DATA_W-1-1));
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va_AluInQ(0) := (others => '0');
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va_AluInQ(0)(0) := '1';
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-- stage 0 calculations
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va_AluOut(0) := va_AluInR(0) - va_AluInQ(0);
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-- stage 0 result registers, ALU output
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a_data(0) <= shift_left(unsigned(iv_data), 2);
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a_R(0) <= (others => '0');
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a_R(0)(G_DATA_W-1 downto G_DATA_W-1-1) <= va_AluOut(0)(1 downto 0);
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a_Q(0) <= (others => '0');
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a_Q(0)(0) <= not va_AluOut(0)(2);
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nextOp(0) <= not va_AluOut(0)(2);
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-- next stages
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for i in 1 to C_PIPE_L-1 loop
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-- prepare inputs for next stage
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va_AluInR(i) := (others => '0');
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va_AluInR(i)(C_OFFSET+i-1 downto 2) := a_R(i-1)(G_DATA_W-(i-1)-1 downto G_DATA_W-(2*i));
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va_AluInR(i)(2-1 downto 0) := a_data(i-1)(G_DATA_W-1 downto G_DATA_W-1-1);
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va_AluInQ(i) := (others => '0');
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va_AluInQ(i)(C_OFFSET+(i-1)-1 downto 2) := a_Q(i-1)(i-1 downto 0);
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va_AluInQ(i)(1) := not a_Q(i-1)(0);
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va_AluInQ(i)(0) := '1';
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-- ALU ADD/SUB
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if (nextOp(i-1) = '1') then
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va_AluOut(i) := va_AluInR(i) - va_AluInQ(i);
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else
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va_AluOut(i) := va_AluInR(i) + va_AluInQ(i);
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end if;
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-- result registers
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a_data(i) <= shift_left(unsigned(a_data(i-1)), 2);
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a_R(i) <= (others => '0');
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a_R(i)(G_DATA_W-i-1 downto G_DATA_W-2*(i+1)) <= va_AluOut(i)(i+1 downto 0);
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a_Q(i) <= shift_left(unsigned(a_Q(i-1)), 1);
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a_Q(i)(0) <= not va_AluOut(i)(i+2);
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nextOp(i) <= not va_AluOut(i)(i+2);
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end loop;
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end if;
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end process;
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ov_res <= std_logic_vector(a_Q(C_PIPE_L-1));
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end architecture squareRoot_pipe_rtl;
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89
U4_FSM/test_fsm.vhd
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U4_FSM/test_fsm.vhd
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------------------------------------------------------------------------
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-- fft_magnitude_calc
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--
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-- calculation of FFT magnitude sqrt(real_part²+im_part²)
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-- Inputs:
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-- input_re in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
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-- input_im in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
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-- input_valid: high = inputs are valid for data processing
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-- Outputs
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-- output_magnitude: Fixpoint 0.5=0x40000000 (always positive)
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-- output_valid: high = magnitude data is valid
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_fft_magnitude_calc is
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generic( GUI_MODE : boolean; CHECK_RESULTS : boolean );
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end entity tb_fft_magnitude_calc;
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architecture rtl of tb_fft_magnitude_calc is
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signal clk : std_logic := '0'; -- Takt
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signal reset : std_logic := '1'; -- Reset
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signal input_valid: std_logic := '0'; -- Eingangsdaten gültig
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signal input_re : std_logic_vector( 31 downto 0 ) := X"40000000"; -- Realteil in Fixpoint
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signal input_im : std_logic_vector( 31 downto 0 ):= X"40000000"; -- Imaginärteil in Fixpoint
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signal output_valid : std_logic; -- Ausgangsdaten gültig
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signal output_magnitude : std_logic_vector( 31 downto 0 );
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begin
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clk <= not clk after 10 ns;
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reset_release : process is
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begin
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wait for 435 ns;
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reset <= '0';
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wait;
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end process reset_release;
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-- Instanziierung des SQRT Moduls für die Berechnung der Quardratwurzel
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-- Weisen Sie die Signale output_sqrt, reset, input_sqrt und clk richtig zu
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fft_magnitude_calc_module : entity work.fft_magnitude_calc
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port map (
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clk => clk,
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reset => reset,
|
||||||
|
input_valid => input_valid, -- Eingangsdaten gültig
|
||||||
|
input_re => input_re, -- Realteil in Fixpoint
|
||||||
|
input_im => input_im, -- Imaginärteil in Fixpoint
|
||||||
|
output_valid => output_valid, -- Ausgangsdaten gültig
|
||||||
|
output_magnitude => output_magnitude -- Berechnete magnitude
|
||||||
|
);
|
||||||
|
|
||||||
|
stimulus: process is
|
||||||
|
begin
|
||||||
|
wait until falling_edge( reset );
|
||||||
|
wait until falling_edge( clk );
|
||||||
|
input_valid <= '1';
|
||||||
|
wait until falling_edge( clk );
|
||||||
|
input_valid <= '0';
|
||||||
|
|
||||||
|
wait until falling_edge( output_valid );
|
||||||
|
|
||||||
|
wait for 200 ns;
|
||||||
|
|
||||||
|
wait until falling_edge( clk );
|
||||||
|
input_valid <= '1';
|
||||||
|
input_re <= X"20000000";
|
||||||
|
input_im <= X"20000000";
|
||||||
|
wait until falling_edge( clk );
|
||||||
|
input_valid <= '0';
|
||||||
|
|
||||||
|
wait until falling_edge( output_valid );
|
||||||
|
|
||||||
|
|
||||||
|
wait until falling_edge( clk );
|
||||||
|
if ( GUI_MODE ) then
|
||||||
|
std.env.stop;
|
||||||
|
else
|
||||||
|
std.env.finish;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process stimulus;
|
||||||
|
|
||||||
|
end architecture rtl;
|
3
U4_FSM/vsim.wave
Normal file
3
U4_FSM/vsim.wave
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
onerror {resume}
|
||||||
|
quietly WaveActivateNextPane {} 0
|
||||||
|
add wave -noupdate /tb_fft_magnitude_calc/fft_magnitude_calc_module/*
|
Loading…
x
Reference in New Issue
Block a user