commit b4e75e651cb18f4627fb6bc48d22b22e38225df7
Author: kutningjo <kutningjo@efiapps0.ads1.fh-nuernberg.de>
Date:   Tue Oct 15 08:26:22 2024 +0200

    initial commit

diff --git a/U1_Datentypen/DataTypesExample.vhd b/U1_Datentypen/DataTypesExample.vhd
new file mode 100644
index 0000000..9d3b882
--- /dev/null
+++ b/U1_Datentypen/DataTypesExample.vhd
@@ -0,0 +1,49 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;     -- Fuer std_logic und std_logic_vector
+use IEEE.NUMERIC_STD.ALL;        -- Fuer signed und unsigned Datentypen
+
+entity DataTypesExample is
+    port (
+        input_slv : in std_logic_vector(7 downto 0);        -- std_logic_vector Eingang
+        output_slv_calc : out std_logic_vector(7 downto 0); -- std_logic_vector Ausgang (Ergebnis einer Berechnuung)
+        output_slv_mask : out std_logic_vector(7 downto 0); -- std_logic_vector Ausgang (Ergebnis einer Maksierung)
+        output_slv_set : out std_logic_vector(7 downto 0)   -- std_logic_vector Ausgang (Setzvorgang)
+    );
+end DataTypesExample;
+
+architecture Behavioral of DataTypesExample is
+    -- constant/signal Deklarationen
+
+    --Legen Sie ein Konstante DataWidth als integer mit Wert 8 an
+
+    --Legen Sie ein Konstante on als std_logic mit 1 an
+
+    --Legen Sie ein Konstante mask als std_logic_vector mit 5Ah an
+
+    --Legen Sie ein signal internal_int als integer mit Wertebreich -128 to 127 an
+
+    --Legen Sie ein signal internal_int als integer mit Wertebreich -128 to 127 an
+
+    --Legen Sie ein signal internal_slv als std_logic_vector mit Laenge 8 an
+
+    --Legen Sie ein signal internal_s als signed mit Laenge 8 an
+
+
+begin
+
+   -- Maskieren (UND) Sie den Eingang input_slv mit der Maske mask und weisen Sie den Wert dem Ausgang output_slv_mask zu
+
+   -- Der Wert des Ausgangs output_slv_set soll dem Eingang input_slv entsprechen wobei immer das 5 Bit (von 8 Bit) per Bitverkettung gesetzt sein soll
+   -- Koonstante one kann verwendet werden
+
+   -- Weisen Sie dem signal internal_slv dein Eingang input_slv zu
+
+   -- Weisen Sie dem signal internal_int das Signal internal_slv zu (Datentypen beachten Konvetierung noetig, mit Vorzeichen)
+
+   -- Rechnen Sie die Subtraktion internal_int - der Konstante eight und weisen Sie das Ergebnis internal_int2 zu
+
+   -- Weisen Sie dem signal das Signal internal_int2 zu (Datentypen beachten Konvetierung noetig)
+
+   -- Weisen Sie dem Ausgang output_slv_calc das signal internal_s zu (Datentypen beachten Konvetierung noetig)
+
+end Behavioral;
diff --git a/U1_Datentypen/Makefile b/U1_Datentypen/Makefile
new file mode 100644
index 0000000..f26ae91
--- /dev/null
+++ b/U1_Datentypen/Makefile
@@ -0,0 +1,10 @@
+
+vhdl_srcs = DataTypesExample.vhd \
+			test_DataTypesExample.vhd \
+
+main = test_DataTypesExample
+
+CHECK_RESULTS = true
+
+include ../scripts/vhdl.mk
+
diff --git a/U1_Datentypen/test_DataTypesExample.vhd b/U1_Datentypen/test_DataTypesExample.vhd
new file mode 100644
index 0000000..e907489
--- /dev/null
+++ b/U1_Datentypen/test_DataTypesExample.vhd
@@ -0,0 +1,33 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+library std;
+    use std.env.all;
+
+entity test_DataTypesExample is
+    generic( CHECK_RESULTS : boolean );
+end entity test_DataTypesExample;
+
+architecture test of test_DataTypesExample is
+    signal input_slv       : std_logic_vector(7 downto 0);
+    signal output_slv_calc : std_logic_vector(7 downto 0);
+    signal output_slv_mask : std_logic_vector(7 downto 0);
+    signal output_slv_set  : std_logic_vector(7 downto 0);
+begin
+    u_DataTypesExample : entity work.DataTypesExample
+        port map (
+            input_slv       => input_slv,
+            output_slv_calc => output_slv_calc,
+            output_slv_mask => output_slv_mask,
+            output_slv_set  => output_slv_set
+        );
+
+    input_slv <= x"5a";
+
+    delay : process
+    begin
+        wait for 100 ns;
+        stop;
+    end process delay;
+
+end architecture test;
diff --git a/U1_Datentypen/test_DataTypesExample.wave b/U1_Datentypen/test_DataTypesExample.wave
new file mode 100644
index 0000000..e6e10ee
--- /dev/null
+++ b/U1_Datentypen/test_DataTypesExample.wave
@@ -0,0 +1,2 @@
+$ version 1.1
+/test_DataTypesExample/u_DataTypesExample/*
diff --git a/U1_Datentypen/vsim.wave b/U1_Datentypen/vsim.wave
new file mode 100644
index 0000000..5c45536
--- /dev/null
+++ b/U1_Datentypen/vsim.wave
@@ -0,0 +1,3 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /test_DataTypesExample/u_DataTypesExample/*
diff --git a/U2_Entity_Component/.test_top_entity.vhd.swp b/U2_Entity_Component/.test_top_entity.vhd.swp
new file mode 100644
index 0000000..8502df7
Binary files /dev/null and b/U2_Entity_Component/.test_top_entity.vhd.swp differ
diff --git a/U2_Entity_Component/Makefile b/U2_Entity_Component/Makefile
new file mode 100644
index 0000000..1d8289a
--- /dev/null
+++ b/U2_Entity_Component/Makefile
@@ -0,0 +1,11 @@
+
+vhdl_srcs = down_counter_int.vhd \
+            top_entity.vhd \
+            test_top_entity.vhd \
+
+main = test_top_entity
+
+CHECK_RESULTS = true
+
+include ../scripts/vhdl.mk
+
diff --git a/U2_Entity_Component/down_counter_int.vhd b/U2_Entity_Component/down_counter_int.vhd
new file mode 100644
index 0000000..5d7a678
--- /dev/null
+++ b/U2_Entity_Component/down_counter_int.vhd
@@ -0,0 +1,31 @@
+library ieee;  
+use ieee.std_logic_1164.all;  
+use ieee.numeric_std.all;  
+  
+entity Backward_Counter is  
+    port (  
+        CLK : in std_logic;             -- Eingangssignal fuer den Takt  
+        RESET : in std_logic;           -- Eingangssignal zum Zuruecksetzen des Zaehlers  
+        INITIAL_VALUE : in integer range 0 to 127;  -- Anfangswert fuer den Zaehler  
+        COUNT_OUT : out integer range 0 to 127     -- Ausgangssignal fuer den aktuellen Zaehlerstand  
+    );  
+end Backward_Counter;  
+  
+architecture Behavioral of Backward_Counter is  
+    signal count : integer range 0 to 127;   -- Signal fuer den Zaehler  
+begin  
+    process(CLK, RESET)  
+    begin  
+        if RESET = '1' then                -- Wenn RESET aktiv ist  
+            count <= INITIAL_VALUE;        -- setze den Zaehler auf den Anfangswert  
+        elsif rising_edge(CLK) then         -- Bei steigender Taktflanke  
+            if count = 0 then               -- Wenn der Zaehlerstand 0 ist  
+                count <= 127;               -- setze den Zaehlerstand auf den maximalen Wert (127)  
+            else  
+                count <= count - 1;         -- Verringere den Zaehlerstand um 1  
+            end if;  
+        end if;  
+    end process;  
+  
+    COUNT_OUT <= count;                    -- Weise den aktuellen Zaehlerstand dem Ausgangssignal zu  
+end Behavioral;  
\ No newline at end of file
diff --git a/U2_Entity_Component/test_top_entity.vhd b/U2_Entity_Component/test_top_entity.vhd
new file mode 100644
index 0000000..e109d7e
--- /dev/null
+++ b/U2_Entity_Component/test_top_entity.vhd
@@ -0,0 +1,42 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+library std;
+    use std.env.all;
+
+entity test_top_entity is
+    generic( CHECK_RESULTS : boolean );
+end entity test_top_entity;
+
+architecture test of test_top_entity is
+    signal CLK   : std_logic := '0';
+    signal RESET : std_logic := '1';
+    signal CNT   : std_logic_vector(6 downto 0);
+begin
+    u_top_entity : entity work.top_entity
+        port map (
+            CLK   => CLK,
+            RESET => RESET,
+            CNT   => CNT
+        );
+
+    CLK <= not CLK after 10 ns;
+
+    p_reset : process( CLK )
+    begin
+        if falling_edge( CLK ) then
+            RESET <= '0';
+        end if;
+    end process p_reset;
+
+    p_run : process
+    begin
+	wait until falling_edge( RESET );
+        for i in 0 to 128 loop
+	    wait until rising_edge( CLK );
+        end loop;
+        wait until rising_edge( CLK );
+	stop;
+    end process p_run;
+
+end architecture test;
diff --git a/U2_Entity_Component/test_top_entity.wave b/U2_Entity_Component/test_top_entity.wave
new file mode 100644
index 0000000..e6e10ee
--- /dev/null
+++ b/U2_Entity_Component/test_top_entity.wave
@@ -0,0 +1,2 @@
+$ version 1.1
+/test_DataTypesExample/u_DataTypesExample/*
diff --git a/U2_Entity_Component/top_entity.vhd b/U2_Entity_Component/top_entity.vhd
new file mode 100644
index 0000000..159a82f
--- /dev/null
+++ b/U2_Entity_Component/top_entity.vhd
@@ -0,0 +1,29 @@
+library ieee;  
+use ieee.std_logic_1164.all;  
+use ieee.numeric_std.all;  
+  
+entity top_entity is  
+    port (  
+        CLK   : in std_logic;                   -- Eingangssignal fuer den Takt  
+        RESET : in std_logic;                   -- Eingangssignal zum Zuruecksetzen des Zaehlers  
+        CNT : out std_logic_vector(6 downto 0)  -- Ausgangssignal fuer den aktuellen Zaehlerstand  
+    );  
+end top_entity;  
+  
+architecture Behavioral of top_entity is  
+
+    -- Legen Sie eine Konstante mit den Wert 57 an, welche Sie der Komponente Backward_Counter als INITIAL_VALUE uebergeben koennen
+
+    -- Legen Sie ein Signal an um das Ergebnis aus COUNT_OUT der Komponente entgegenzunehmen zu koennen
+	
+begin  
+
+    -- Instanzieren Sie direkt die Backward_Counter Komponente
+	-- Als Takt und Reset sollen die jeweiligen Eingaenge der top_entity uebergeben werden
+	-- Als Anfangswert fuer den Zaehler Ihre angelegte Konstante
+	-- Der aktuelle Zaehlerstand soll Ihrem angelegten signal uebergeben werden
+
+  		  
+    -- Machhen Sie eine Zuweisung damit der Ausgang CNT der top_entity dem aktuellen Zaehlerstand entspricht
+
+end Behavioral;  
diff --git a/U2_Entity_Component/vsim.wave b/U2_Entity_Component/vsim.wave
new file mode 100644
index 0000000..689218d
--- /dev/null
+++ b/U2_Entity_Component/vsim.wave
@@ -0,0 +1,3 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /test_top_entity/u_top_entity/*
diff --git a/U4_FSM/Makefile b/U4_FSM/Makefile
new file mode 100644
index 0000000..1d8289a
--- /dev/null
+++ b/U4_FSM/Makefile
@@ -0,0 +1,11 @@
+
+vhdl_srcs = down_counter_int.vhd \
+            top_entity.vhd \
+            test_top_entity.vhd \
+
+main = test_top_entity
+
+CHECK_RESULTS = true
+
+include ../scripts/vhdl.mk
+
diff --git a/scripts/check_test_results.sh b/scripts/check_test_results.sh
new file mode 100755
index 0000000..e77051c
--- /dev/null
+++ b/scripts/check_test_results.sh
@@ -0,0 +1,15 @@
+#!/bin/bash
+script_dir=$(cd $(dirname "${BASH_SOURCE[0]}") && pwd)
+
+if [ $# -ne 1 ]
+then
+    echo Usage $0 test-output-file
+    exit 1
+fi
+
+cat $1 | sed -z -e 's/\(py_.* \[\)/ \[/g' | ${script_dir}/highlight_test_results.sh
+
+if grep -q FAIL $1
+then
+    exit 1
+fi
diff --git a/scripts/execute_and_highlight.sh b/scripts/execute_and_highlight.sh
new file mode 100755
index 0000000..851117c
--- /dev/null
+++ b/scripts/execute_and_highlight.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+script_path="$( dirname  "$( readlink -f "${BASH_SOURCE[0]}" )" )"
+
+if [ $# -lt 1 ]
+then
+    echo " usage: execute_and_highlight command arguments"
+    exit 1
+fi
+
+cmd=$1
+shift 1
+$cmd $@ | $script_path/highlight_test_results.sh
+test ${PIPESTATUS[0]} -eq 0
+
diff --git a/scripts/ghdl.mk b/scripts/ghdl.mk
new file mode 100644
index 0000000..cc679c2
--- /dev/null
+++ b/scripts/ghdl.mk
@@ -0,0 +1,64 @@
+#
+#
+#
+#
+
+# Make sure that the top level is assigned to main
+$(if $(main),,\
+$(error Assign top level entity name to variable "main"))
+
+# Make sure that at least on vhdl source is assigned
+$(if $(vhdl_srcs),,\
+$(error Assign at least on vhdl source to variable "vhdl_srcs"))
+
+# Append prefix -d to all generics
+generics  = $(addprefix -g,$(generics))
+
+# Add VHDL 2008 as default build standard
+vhdl_flags += --std=08
+vhdl_flags += -frelaxed-rules
+#vhdl_flags += --ieee-asserts=disable-at-0
+
+vhdl_objs = $(vhdl_srcs:.vhd=.o)
+
+assert_level := error
+
+.PHONY: sim clean
+
+sim: ${main}
+	@../scripts/execute_and_highlight.sh \
+		ghdl \
+		-r ${vhdl_flags} ${main} \
+		-gCHECK_RESULTS=${CHECK_RESULTS} \
+		--read-wave-opt=${main}.wave \
+		--assert-level=${assert_level}
+
+gui: ${main}.ghw
+	@echo "Viewing $<"
+	@gtkwave $< --script=gtkwave.view
+
+${main}.ghw: ${main} ${main}.wave
+	@ghdl -r ${vhdl_flags} ${main} \
+		--read-wave-opt=${main}.wave \
+		--wave=$@
+
+${main}: $(vhdl_objs)
+	@echo "Elaborating ${main}"
+	@ghdl -e ${vhdl_flags} ${main}
+
+%.o: %.vhd
+	@echo "Analysing $<"
+	@ghdl -a ${vhdl_flags} $<
+
+clean:
+	@ghdl --clean
+	@rm -rf ${main}.ghw work-obj08.cf ${vhdl_objs} ${main} ${artifacts}
+
+help:
+	@echo Use ghdl to simulate and synthesis a vhdl design.
+	@echo
+	@echo Build configuration variables:
+	@echo 	main        main entity
+	@echo 	vhdl_flags
+	@echo 	generics
+
diff --git a/scripts/highlight_test_results.sh b/scripts/highlight_test_results.sh
new file mode 100755
index 0000000..eb1066a
--- /dev/null
+++ b/scripts/highlight_test_results.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+red=$(tput setaf 1)
+green=$(tput setaf 2)
+default=$(tput sgr0)
+
+sed "s/FAIL/${red}FAIL${default}/" | sed "s/OK/${green}OK${default}/"
diff --git a/scripts/questa-sim.mk b/scripts/questa-sim.mk
new file mode 100644
index 0000000..d1b32d3
--- /dev/null
+++ b/scripts/questa-sim.mk
@@ -0,0 +1,64 @@
+#
+#
+#
+#
+
+# Make sure that the top level is assigned to main
+$(if $(main),,\
+$(error Assign top level entity name to variable "main"))
+
+# Make sure that at least on vhdl source is assigned
+$(if $(vhdl_srcs),,\
+$(error Assign at least on vhdl source to variable "vhdl_srcs"))
+
+# Add VHDL 2008 as default build standard
+vhdl_flags += -2008
+
+vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
+verilog_objs = $(verilog_srcs:.v=.vo)
+
+assert_level := error
+
+.PHONY: sim clean
+
+gui: ${verilog_objs} ${vhdl_objs}
+	@vsim \
+		-gCHECK_RESULTS=$(CHECK_RESULTS) \
+		-voptargs=+acc work.${main} -do "do vsim.wave; run -all"
+
+sim: ${verilog_objs} ${vhdl_objs}
+	@vsim \
+		-gCHECK_RESULTS=$(CHECK_RESULTS) \
+	       	-voptargs=+acc -c work.${main} -do "run -all" \
+	 	| ../scripts/highlight_test_results.sh
+
+%.vo: %.v .libwork
+	@echo "Analysing $<"
+	@vlog -work work ${verilog_flags} $<
+
+%.vhdo: %.vhd .libwork
+	@echo "Analysing $<"
+	@vcom -work work ${vhdl_flags} $<
+
+
+.libwork:
+	@vlib work && vmap work work && touch $@
+
+clean:
+	@rm -rf work \
+	 .libwork \
+	 transcript \
+	 modelsim.ini \
+	 vlog.opt \
+	 vsim.wlf \
+	 data.py \
+	 data.pyc \
+
+help:
+	@echo Use ghdl to simulate and synthesis a vhdl design.
+	@echo
+	@echo Build configuration variables:
+	@echo 	main        main entity
+	@echo 	vhdl_flags
+	@echo 	generics
+
diff --git a/scripts/vhdl.mk b/scripts/vhdl.mk
new file mode 100644
index 0000000..73a7c79
--- /dev/null
+++ b/scripts/vhdl.mk
@@ -0,0 +1,23 @@
+
+ghdl_version = $(shell ghdl --version 2> /dev/null)
+vsim_version = $(shell vsim -version 2> /dev/null)
+
+# in case verilog is part of the build a verilog capable simulator is required
+ifdef verilog_srcs
+ifneq (${vsim_version},)
+include ../scripts/questa-sim.mk
+else
+$(error No HDL simulation tool found for verilog!)
+endif
+else
+ifneq (${vsim_version},)
+include ../scripts/questa-sim.mk
+else
+ifneq (${ghdl_version},)
+include ../scripts/ghdl.mk
+else
+$(error No HDL simulation tool found!)
+endif
+endif
+endif
+