Initial commit

u2/test/tb_top_entity_float_add.vhd

@@ -0,0 +1,85 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+library std;
+    use std.env.all;
+
+library work;
+    use work.test_utility.all;
+
+entity tb_top_entity_float_add is
+    generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := true );
+end;
+
+architecture test of tb_top_entity_float_add is
+    signal clk           : std_logic := '0';
+    signal reset         : std_logic := '1';
+    signal run_calc      : std_logic := '0';
+    signal operand_a     : std_logic_vector(31 downto 0) := ( others => '0' );
+    signal operand_b     : std_logic_vector(31 downto 0) := ( others => '0' );
+    signal result        : std_logic_vector(31 downto 0);
+    signal calc_complete : std_logic;
+begin
+
+    u_top_entity_float_add : entity work.top_entity_float_add
+        port map (
+            clk           => clk,
+            reset         => reset,
+            run_calc      => run_calc,
+            operand_a     => operand_a,
+            operand_b     => operand_b,
+            result        => result,
+            calc_complete => calc_complete
+        );
+
+    a_clk: clk <= not clk after 10 ns;
+
+    a_reset: process( clk )
+    begin
+        if falling_edge( clk ) then
+            reset <= '0';
+        end if;
+    end process;
+
+    delay : process
+        variable res      : std_logic_vector( 31 downto 0 );
+        variable expected : std_logic_vector( 31 downto 0 );
+    begin
+
+        wait until falling_edge( reset );
+
+        -----------------------------------------------------------------------
+        wait until rising_edge( clk );
+        run_calc      <= '1';
+        operand_a     <= x"01000000";
+        operand_b     <= x"02000000";
+        wait until rising_edge( calc_complete );
+        run_calc      <= '0';
+        if ( CHECK_RESULTS ) then
+            res  := result;
+            expected := x"02200000";
+            assert_eq( res, expected );
+        end if;
+        wait until rising_edge( clk );
+
+        -----------------------------------------------------------------------
+        wait until rising_edge( clk );
+        run_calc      <= '1';
+        operand_a     <= x"4048f5c3"; -- 3.14
+        operand_b     <= x"402d70a4"; -- 2.71
+        wait until rising_edge( calc_complete );
+        if ( CHECK_RESULTS ) then
+            res  := result;
+            expected := x"40bb3333"; -- 5.85
+            assert_eq( res, expected );
+        end if;
+        wait until rising_edge( clk );
+
+        if GUI_MODE = true then
+            finish;
+        else
+            stop;
+        end if;
+    end process delay;
+
+end architecture test;