Initial commit

u3/scripts/questa-sim.mk

@@ -0,0 +1,63 @@
+#
+#
+#
+#
+
+# Make sure that the top level is assigned to main
+$(if $(main),,\
+$(error Assign top level entity name to variable "main"))
+
+# Make sure that at least on vhdl source is assigned
+$(if $(vhdl_srcs),,\
+$(error Assign at least on vhdl source to variable "vhdl_srcs"))
+
+# Append prefix -d to all generics
+generics  = $(addprefix -g,$(generics))
+
+# Add VHDL 2008 as default build standard
+vhdl_flags += -2008
+
+vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
+verilog_objs = $(verilog_srcs:.v=.vo)
+
+assert_level := error
+
+.PHONY: sim clean
+
+sim: ${verilog_objs} ${vhdl_objs}
+	@vsim -voptargs=+acc -c work.${main} -g CHECK_RESULTS=true -do "run -all" \
+	 | scripts/highlight_test_results.sh
+
+gui: ${verilog_objs} ${vhdl_objs}
+	@vsim -voptargs=+acc work.${main} -g CHECK_RESULTS=false -do "do test/vsim.wave; run -all"
+
+%.vo: %.v .libwork
+	@echo "Analysing $<"
+	@vlog -work work ${verilog_flags} $<
+
+%.vhdo: %.vhd .libwork
+	@echo "Analysing $<"
+	@vcom -work work ${vhdl_flags} $<
+
+
+.libwork:
+	@vlib work && vmap work work && touch $@
+
+clean:
+	@rm -rf work \
+	 .libwork \
+	 transcript \
+	 modelsim.ini \
+	 vlog.opt \
+	 vsim.wlf \
+	 data.py \
+	 data.pyc \
+
+help:
+	@echo Use ghdl to simulate and synthesis a vhdl design.
+	@echo
+	@echo Build configuration variables:
+	@echo 	main        main entity
+	@echo 	vhdl_flags
+	@echo 	generics
+