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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity float_add is
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port(A : in std_logic_vector(31 downto 0);
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B : in std_logic_vector(31 downto 0);
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clk : in std_logic;
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reset : in std_logic;
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start : in std_logic;
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done : out std_logic;
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sum : out std_logic_vector(31 downto 0)
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);
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end float_add;
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architecture mixed of float_add is
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type ST is (WAIT_STATE, ALIGN_STATE, ADDITION_STATE, NORMALIZE_STATE, OUTPUT_STATE);
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signal state : ST := WAIT_STATE;
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---Internal Signals latched from the inputs
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signal A_mantissa, B_mantissa : std_logic_vector (24 downto 0);
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signal A_exp, B_exp : std_logic_vector (8 downto 0);
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signal A_sgn, B_sgn : std_logic;
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--Internal signals for Output
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signal sum_exp: std_logic_vector (8 downto 0);
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signal sum_mantissa : std_logic_vector (24 downto 0);
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signal sum_sgn : std_logic;
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begin
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Control_Unit : process (clk, reset) is
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variable diff : signed(8 downto 0);
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begin
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if(reset = '1') then
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state <= WAIT_STATE; --start in wait state
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done <= '0';
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elsif rising_edge(clk) then
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case state is
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when WAIT_STATE =>
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if (start = '1') then --wait till start request startes high
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A_sgn <= A(31);
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A_exp <= '0' & A(30 downto 23); --One bit is added for signed subtraction
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A_mantissa <= "01" & A(22 downto 0); --Two bits are added extra, one for leading 1 and other one for storing carry
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B_sgn <= B(31);
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B_exp <= '0' & B(30 downto 23);
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B_mantissa <= "01" & B(22 downto 0);
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state <= ALIGN_STATE;
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else
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state <= WAIT_STATE;
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end if;
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when ALIGN_STATE => --Compare exponent and align it
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--If any num is greater by 2**24, we skip the addition.
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if unsigned(A_exp) > unsigned(B_exp) then
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--B needs downshifting
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diff := signed(A_exp) - signed(B_exp); --Small Alu
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if diff > 23 then
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sum_mantissa <= A_mantissa; --B insignificant relative to A
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sum_exp <= A_exp;
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sum_sgn <= A_sgn;
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state <= OUTPUT_STATE; --start latch A as output
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else
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--downshift B to equilabrate B_exp to A_exp
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sum_exp <= A_exp;
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B_mantissa(24-to_integer(diff) downto 0) <= B_mantissa(24 downto to_integer(diff));
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B_mantissa(24 downto 25-to_integer(diff)) <= (others => '0');
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state <= ADDITION_STATE;
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end if;
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elsif unsigned(A_exp) < unsigned(B_exp) then --A_exp < B_exp. A needs downshifting
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diff := signed(B_exp) - signed(A_exp); -- Small Alu
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if diff > 23 then
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sum_mantissa <= B_mantissa; --A insignificant relative to B
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sum_sgn <= B_sgn;
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sum_exp <= B_exp;
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state <= OUTPUT_STATE; --start latch B as output
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else
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--downshift A to equilabrate A_exp to B_exp
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sum_exp <= B_exp;
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A_mantissa(24-to_integer(diff) downto 0) <= A_mantissa(24 downto to_integer(diff));
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A_mantissa(24 downto 25-to_integer(diff)) <= (others => '0');
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state <= ADDITION_STATE;
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end if;
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else -- Both exponent is equal. No need to mantissa shift
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sum_exp <= A_exp;
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state <= ADDITION_STATE;
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end if;
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when ADDITION_STATE => --Mantissa addition
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state <= NORMALIZE_STATE;
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if (A_sgn xor B_sgn) = '0' then --signs are the same. Just add them
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sum_mantissa <= std_logic_vector((unsigned(A_mantissa) + unsigned(B_mantissa))); --Big Alu
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sum_sgn <= A_sgn; --both nums have same sign
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--Else subtract smaller from larger and use sign of larger
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elsif unsigned(A_mantissa) >= unsigned(B_mantissa) then
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sum_mantissa <= std_logic_vector((unsigned(A_mantissa) - unsigned(B_mantissa))); --Big Alu
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sum_sgn <= A_sgn;
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else
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sum_mantissa <= std_logic_vector((unsigned(B_mantissa) - unsigned(A_mantissa))); --Big Alu
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sum_sgn <= B_sgn;
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end if;
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when NORMALIZE_STATE => --Normalization.
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if unsigned(sum_mantissa) = TO_UNSIGNED(0, 25) then
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--The sum is 0
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sum_mantissa <= (others => '0');
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sum_exp <= (others => '0');
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state <= OUTPUT_STATE;
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elsif(sum_mantissa(24) = '1') then --If sum overflowed we downshift and are done.
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sum_mantissa <= '0' & sum_mantissa(24 downto 1); --shift the 1 down
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sum_exp <= std_logic_vector((unsigned(sum_exp)+ 1));
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state <= OUTPUT_STATE;
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elsif(sum_mantissa(23) = '0') then --in this case we need to upshift
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--This iterates the normalization shifts, thus can take many clocks.
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sum_mantissa <= sum_mantissa(23 downto 0) & '0';
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sum_exp <= std_logic_vector((unsigned(sum_exp)-1));
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state<= NORMALIZE_STATE; --keep shifting till leading 1 appears
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else
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state <= OUTPUT_STATE; --leading 1 already there. Latch output
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end if;
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when OUTPUT_STATE =>
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sum(22 downto 0) <= sum_mantissa(22 downto 0);
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sum(30 downto 23) <= sum_exp(7 downto 0);
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sum(31) <= sum_sgn;
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done <= '1'; -- signal done
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if (start = '0') then -- stay in the state till request ends i.e start is low
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done <= '0';
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state <= WAIT_STATE;
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end if;
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when others =>
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state <= WAIT_STATE; --Just in case.
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end case;
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end if;
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end process;
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end mixed;
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