Initial commit

u3/test/tb_fsm_add.vhd

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+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.float_pkg.all;
+
+library work;
+    use work.test_utility.all;
+    use work.sine_data.all;
+    use work.cosine_data.all;
+    use work.sine_cosine_data.all;
+
+library std;
+    use std.env.all;
+    use std.textio.all;
+
+entity tb_fsm_add is
+    generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := true );
+end;
+
+architecture test of tb_fsm_add is
+    signal clk               : std_logic := '0';
+    signal reset             : std_logic := '1';
+    signal run_calc          : std_logic;
+    signal calc_cnt          : std_logic_vector( 3 downto 0 );
+
+    signal signal_a_read     : std_logic;
+    signal signal_a_readdata : std_logic_vector( 31 downto 0 );
+
+    signal signal_b_read     : std_logic;
+    signal signal_b_readdata : std_logic_vector( 31 downto 0 );
+
+    signal signal_write      : std_logic;
+    signal signal_writedata  : std_logic_vector( 31 downto 0 );
+
+begin
+
+    u_fsm_add : entity work.fsm_add
+        port map (
+             clk               => clk,
+             reset             => reset,
+             run_calc          => run_calc,
+             calc_cnt          => calc_cnt,
+
+             signal_a_read     => signal_a_read,
+             signal_a_readdata => signal_a_readdata,
+
+             signal_b_read     => signal_b_read,
+             signal_b_readdata => signal_b_readdata,
+
+             signal_write      => signal_write,
+             signal_writedata  => signal_writedata
+         );
+
+    a_clk: clk <= not clk after 10 ns;
+
+    a_reset: process( clk )
+    begin
+        if falling_edge( clk ) then
+            reset <= '0';
+        end if;
+    end process;
+
+    input_data_a_simulus: process is
+        variable index : integer := 0;
+    begin
+        while true loop
+            signal_a_readdata <= to_std_logic_vector( to_float( work.sine_data.expected( index ) ) );
+            wait until rising_edge( signal_a_read );
+            if ( index < 1023 ) then
+                index := index + 1;
+            end if;
+        end loop;
+    end process input_data_a_simulus;
+
+    input_data_b_simulus: process is
+        variable index : integer := 0;
+    begin
+        while true loop
+            signal_b_readdata <= to_std_logic_vector( to_float( work.cosine_data.expected( index ) ) );
+            wait until rising_edge( signal_b_read );
+            if ( index < 1023 ) then
+                index := index + 1;
+            end if;
+        end loop;
+    end process input_data_b_simulus;
+
+    stimulus: process is
+        variable expected : real;
+        variable float_value : float32;
+        variable real_value : real;
+        variable abs_err : real := 0.5e-1;
+    begin
+        std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );
+        std.textio.write( std.textio.OUTPUT, "Starting tb_fsm_add" & LF );
+        wait until falling_edge( reset );
+
+        wait until falling_edge( clk );
+        run_calc <= '1';
+        wait until falling_edge( clk );
+
+        for i in 0 to 16 loop
+            wait until rising_edge( signal_write );
+            expected := work.sine_cosine_data.expected( i + 1 );
+            float_value := to_float( signal_writedata );
+            real_value := to_real( float_value );
+            assert_near( real_value, expected, abs_err );
+        end loop;
+
+        if GUI_MODE = true then
+            finish;
+        else
+            stop;
+        end if;
+    end process stimulus;
+
+end architecture test;