vhdl_einfuehrung/U3_Anweisungen/test_alu.vhd

library ieee;
    use ieee.std_logic_1164.all;

library std;
    use std.env.all;
    use std.textio.all;

library work;
    use work.test_utility.all;

entity test_alu is
    generic( GUI_MODE : boolean; CHECK_RESULTS : boolean );
end entity test_alu;

architecture test of test_alu is
    signal clk           : std_logic := '0';
    signal reset         : std_logic := '1';
    signal operand_a     : std_logic_vector(3 downto 0);
    signal operand_b     : std_logic_vector(3 downto 0);
    signal opcode        : std_logic_vector(1 downto 0);
    signal result_out    : std_logic_vector(3 downto 0);
    signal flag_zero_out : std_logic;
    signal flag_or_out   : std_logic;
begin
    u_alu : entity work.SimpleALU
        port map (
            clk           =>  clk,
            reset         =>  reset,
            operand_a     =>  operand_a,
            operand_b     =>  operand_b,
            opcode        =>  opcode,
            result_out    =>  result_out,
            flag_zero_out =>  flag_zero_out,
            flag_or_out   =>  flag_or_out
        );

    clk <= not clk after 10 ns;

    p_reset : process( clk )
    begin
        if falling_edge( clk ) then
            reset <= '0';
        end if;
    end process p_reset;

    p_run : process
    begin
        wait until falling_edge( reset );
        -- Addition
        write( output, "Test Addition ... " );
        opcode <= "00";
        operand_a <= x"a";
        operand_b <= x"5"; 
        wait until falling_edge( clk );
        wait until falling_edge( clk );
        assert_eq( result_out, x"f" );
        assert_eq( flag_zero_out, '0' );
        assert_eq( flag_or_out, '0' );
        write( output, "done" & LF );

        -- Subtraktion auf Null
        write( output, "Test Subtraktion ... " );
        opcode <= "01";
        operand_a <= x"a";
        operand_b <= x"a"; 
        wait until falling_edge( clk );
        wait until falling_edge( clk );
        assert_eq( result_out, x"0" );
        assert_eq( flag_zero_out, '1' );
        assert_eq( flag_or_out, '0' );
        write( output, "done" & LF );

        -- UND-Operation
        write( output, "Test UND-Operation ... " );
        opcode <= "10";
        operand_a <= x"a";
        operand_b <= x"3"; 
        wait until falling_edge( clk );
        wait until falling_edge( clk );
        assert_eq( result_out, x"2" );
        assert_eq( flag_zero_out, '0' );
        assert_eq( flag_or_out, '0' );
        write( output, "done" & LF );

        -- ODER-Operation
        write( output, "Test ODER-Operation ... " );
        opcode <= "11";
        operand_a <= x"a";
        operand_b <= x"3"; 
        wait until falling_edge( clk );
        wait until falling_edge( clk );
        assert_eq( result_out, x"b" );
        assert_eq( flag_zero_out, '0' );
        assert_eq( flag_or_out, '1' );
        write( output, "done" & LF );

        wait until falling_edge( clk );
        if ( GUI_MODE ) then
            std.env.stop;
        else
            std.env.finish;
        end if;
    end process p_run;

end architecture test;