vhdl_einfuehrung/U2_Entity_Component/test_top_entity.vhd

library ieee;
    use ieee.std_logic_1164.all;

library std;
    use std.env.all;

entity test_top_entity is
    generic( CHECK_RESULTS : boolean );
end entity test_top_entity;

architecture test of test_top_entity is
    signal CLK   : std_logic := '0';
    signal RESET : std_logic := '1';
    signal CNT   : std_logic_vector(6 downto 0);
begin
    u_top_entity : entity work.top_entity
        port map (
            CLK   => CLK,
            RESET => RESET,
            CNT   => CNT
        );

    CLK <= not CLK after 10 ns;

    p_reset : process( CLK )
    begin
        if falling_edge( CLK ) then
            RESET <= '0';
        end if;
    end process p_reset;

    p_run : process
    begin
	wait until falling_edge( RESET );
        for i in 0 to 128 loop
	    wait until rising_edge( CLK );
        end loop;
        wait until rising_edge( CLK );
	stop;
    end process p_run;

end architecture test;