vhdl_einfuehrung/scripts/questa-sim.mk

#
#
#
#

# Make sure that the top level is assigned to main
$(if $(main),,\
$(error Assign top level entity name to variable "main"))

# Make sure that at least on vhdl source is assigned
$(if $(vhdl_srcs),,\
$(error Assign at least on vhdl source to variable "vhdl_srcs"))

# Add VHDL 2008 as default build standard
vhdl_flags += -2008

vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
verilog_objs = $(verilog_srcs:.v=.vo)

assert_level := error

.PHONY: sim clean

gui: ${verilog_objs} ${vhdl_objs}
	@vsim \
		-gCHECK_RESULTS=$(CHECK_RESULTS) \
		-voptargs=+acc work.${main} -do "do vsim.wave; run -all"

sim: ${verilog_objs} ${vhdl_objs}
	@vsim \
		-gCHECK_RESULTS=$(CHECK_RESULTS) \
	       	-voptargs=+acc -c work.${main} -do "run -all" \
	 	| ../scripts/highlight_test_results.sh

%.vo: %.v .libwork
	@echo "Analysing $<"
	@vlog -work work ${verilog_flags} $<

%.vhdo: %.vhd .libwork
	@echo "Analysing $<"
	@vcom -work work ${vhdl_flags} $<


.libwork:
	@vlib work && vmap work work && touch $@

clean:
	@rm -rf work \
	 .libwork \
	 transcript \
	 modelsim.ini \
	 vlog.opt \
	 vsim.wlf \
	 data.py \
	 data.pyc \

help:
	@echo Use ghdl to simulate and synthesis a vhdl design.
	@echo
	@echo Build configuration variables:
	@echo 	main        main entity
	@echo 	vhdl_flags
	@echo 	generics