diff --git a/Makefile b/Makefile
index 8b89545..f30c3de 100644
--- a/Makefile
+++ b/Makefile
@@ -1,10 +1,14 @@
 
-vhdl_srcs = float_add.vhd \
-			top_entity_float_add.vhd \
+vhdl_srcs = test/float_add.vhd \
+			fsm_add.vhd \
+			test/float.vhd \
 			test/test_utility.vhd \
-			test/tb_top_entity_float_add.vhd \
+			test/sine.vhd \
+			test/cosine.vhd \
+			test/sine_cosine.vhd \
+			test/tb_fsm_add.vhd \
 
-main = tb_top_entity_float_add
+main = tb_fsm_add
 
 CHECK_RESULTS = true
 
diff --git a/U2_U3_Beschreibung_ip_core_float_add_.pdf b/U2_U3_Beschreibung_ip_core_float_add_.pdf
deleted file mode 100644
index 6ef1256..0000000
Binary files a/U2_U3_Beschreibung_ip_core_float_add_.pdf and /dev/null differ
diff --git a/test/cosine.vhd b/test/cosine.vhd
new file mode 100644
index 0000000..f208643
--- /dev/null
+++ b/test/cosine.vhd
@@ -0,0 +1,9 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+
+library work;
+    use work.test_utility.all;
+
+package cosine_data is
+    constant expected : real_array( 0 to 1023 ) := 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774758e-01,-6.180339e-01,-5.579821e-01,-4.973796e-01,-4.362863e-01,-3.747624e-01,-3.128687e-01,-2.506662e-01,-1.882164e-01,-1.255807e-01,-6.282119e-02,3.496911e-07,6.282189e-02,1.255814e-01,1.882161e-01,2.506660e-01,3.128684e-01,3.747622e-01,4.362870e-01,4.973803e-01,5.579827e-01,6.180345e-01,6.774764e-01,7.362489e-01,7.942955e-01,8.515584e-01,9.079808e-01,9.635072e-01,1.018083e+00,1.071653e+00,1.124167e+00,1.175571e+00,1.225814e+00,1.274848e+00,1.322624e+00,1.369094e+00,1.414214e+00,1.457937e+00,1.500222e+00,1.541027e+00,1.580310e+00,1.618034e+00,1.654161e+00,1.688656e+00,1.721484e+00,1.752614e+00,1.782013e+00,1.809654e+00,1.835509e+00,1.859553e+00,1.881762e+00,1.902113e+00,1.920587e+00,1.937166e+00,1.951833e+00,1.964575e+00,1.975377e+00,1.984229e+00,1.991124e+00,1.996053e+00,1.999013e+00,2.000000e+00,1.999013e+00,1.996053e+00,1.991124e+00,1.984229e+00,1.975377e+00,1.964574e+00,1.951833e+00,1.937166e+00,1.920587e+00,1.902113e+00,1.881762e+00,1.859553e+00,1.835509e+00,1.809654e+00,1.782013e+00,1.752613e+00,1.721484e+00,1.688656e+00,1.654161e+00,1.618034e+00,1.580310e+00,1.541026e+00,1.500222e+00,1.457937e+00,1.414214e+00,1.369094e+00,1.322624e+00,1.274848e+00,1.225814e+00,1.175570e+00,1.124167e+00,1.071653e+00,1.018083e+00,9.635071e-01,9.079807e-01,8.515583e-01,7.942955e-01,7.362492e-01,6.774759e-01,6.180341e-01,5.579823e-01,4.973798e-01,4.362865e-01,3.747626e-01,3.128689e-01,2.506664e-01,1.882165e-01,1.255809e-01,6.282137e-02,-1.748456e-07,-6.282172e-02,-1.255808e-01,-1.882164e-01,-2.506667e-01,-3.128692e-01,-3.747630e-01,-4.362864e-01,-4.973797e-01,-5.579821e-01,-6.180344e-01,-6.774758e-01,-7.362491e-01,-7.942958e-01,-8.515586e-01,-9.079811e-01,-9.635074e-01,-1.018083e+00,-1.071654e+00,-1.124167e+00,-1.175571e+00,-1.225814e+00,-1.274848e+00,-1.322624e+00,-1.369094e+00,-1.414213e+00,-1.457937e+00,-1.500222e+00,-1.541026e+00,-1.580310e+00,-1.618034e+00,-1.654161e+00,-1.688656e+00,-1.721484e+00,-1.752613e+00,-1.782013e+00,-1.809654e+00,-1.835509e+00,-1.859553e+00,-1.881761e+00,-1.902113e+00,-1.920587e+00,-1.937166e+00,-1.951833e+00,-1.964574e+00,-1.975377e+00,-1.984229e+00,-1.991124e+00,-1.996053e+00,-1.999013e+00,-2.000000e+00,-1.999013e+00,-1.996053e+00,-1.991124e+00,-1.984229e+00,-1.975377e+00,-1.964574e+00,-1.951833e+00,-1.937166e+00,-1.920587e+00,-1.902113e+00,-1.881761e+00,-1.859553e+00,-1.835509e+00,-1.809654e+00,-1.782013e+00,-1.752614e+00,-1.721484e+00,-1.688656e+00,-1.654161e+00,-1.618034e+00,-1.580310e+00,-1.541026e+00,-1.500222e+00,-1.457937e+00,-1.414214e+00,-1.369094e+00,-1.322624e+00,-1.274848e+00,-1.225814e+00,-1.175571e+00,-1.124167e+00,-1.071653e+00,-1.018083e+00,-9.635074e-01,-9.079810e-01,-8.515586e-01,-7.942958e-01,-7.362491e-01,-6.774758e-01,-6.180339e-01,-5.579821e-01,-4.973796e-01,-4.362863e-01,-3.747624e-01,-3.128687e-01,-2.506662e-01,-1.882164e-01,-1.255807e-01,-6.282119e-02,3.496911e-07,6.282189e-02,1.255814e-01,1.882161e-01,2.506660e-01,3.128684e-01,3.747622e-01,4.362870e-01,4.973803e-01,5.579827e-01,6.180345e-01,6.774764e-01,7.362489e-01,7.942955e-01,8.515584e-01,9.079808e-01,9.635072e-01,1.018083e+00,1.071653e+00,1.124167e+00,1.175571e+00,1.225814e+00,1.274848e+00,1.322624e+00,1.369094e+00,1.414214e+00,1.457937e+00,1.500222e+00,1.541027e+00,1.580310e+00,1.618034e+00,1.654161e+00,1.688656e+00,1.721484e+00,1.752614e+00,1.782013e+00,1.809654e+00,1.835509e+00,1.859553e+00,1.881762e+00,1.902113e+00,1.920587e+00,1.937166e+00,1.951833e+00,1.964575e+00,1.975377e+00,1.984229e+00,1.991124e+00,1.996053e+00,1.999013e+00,2.000000e+00,1.999013e+00,1.996053e+00,1.991124e+00,1.984229e+00,1.975377e+00,1.964574e+00,1.951833e+00,1.937166e+00,1.920587e+00,1.902113e+00,1.881762e+00,1.859553e+00,1.835509e+00,1.809654e+00,1.782013e+00,1.752613e+00,1.721484e+00,1.688656e+00,1.654161e+00,1.618034e+00,1.580310e+00,1.541026e+00,1.500222e+00);
+end package cosine_data;
diff --git a/test/float.vhd b/test/float.vhd
new file mode 100644
index 0000000..889f217
--- /dev/null
+++ b/test/float.vhd
@@ -0,0 +1,144 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package float is
+    constant SIGN : std_logic_vector( 31 downto 31 ) := ( others => '0' );
+    constant EXP : std_logic_vector( 30 downto 23 ) := ( others => '0' );
+    constant MANTISSA : std_logic_vector( 22 downto 0 ) := ( others => '0' );
+
+    function find_leftmost( arg : unsigned; value : std_ulogic ) return integer;
+
+    function count_leading_digits( arg : unsigned; value : std_ulogic ) return integer;
+
+    function to_float( arg : std_logic_vector ) return std_logic_vector;
+
+    function to_fixed( arg : std_logic_vector ) return std_logic_vector;
+
+end package float;
+
+package body float is
+    function find_leftmost( arg : unsigned; value : std_ulogic ) return integer is
+    begin
+        for i in arg'left downto arg'right loop
+            if ( arg( i ) = value ) then
+                return i;
+            end if;
+        end loop;
+
+        return -1;
+    end function find_leftmost;
+
+    function count_leading_digits( arg : unsigned; value : std_ulogic ) return integer is
+        variable left_most_value : integer range -1 to arg'high;
+        variable leading_values : integer range 0 to arg'high;
+    begin
+        left_most_value := find_leftmost( arg, not value );
+        leading_values := 0;
+
+        if ( left_most_value /= -1 ) then
+            leading_values := arg'high - left_most_value;
+        end if;
+
+        return leading_values;
+    end function count_leading_digits;
+
+    function to_float( arg : std_logic_vector ) return std_logic_vector is
+        variable y : std_logic_vector( 31 downto 0 );
+        variable s : std_logic;
+        variable e : unsigned( 7 downto 0 );
+        variable m : unsigned( 22 downto 0 );
+        variable value : unsigned( 30 downto 0 );
+
+        variable leading_sign_digits : integer range 0 to value'high;
+        variable reminding : integer range 0 to value'high;
+    begin
+        s := arg( 31 );
+
+        if ( s = '0' ) then
+            value := unsigned( arg( 30 downto 0 ) );
+        else
+            value := not unsigned( arg( 30 downto 0 ) );
+            value := value +1;
+        end if;
+        leading_sign_digits := count_leading_digits( value, '0' );
+        reminding := value'high - leading_sign_digits;
+        e := to_unsigned( 126 - leading_sign_digits, e'length );
+
+        if ( reminding > m'length ) then
+            m := value( reminding - 1 downto reminding - m'length );
+        elsif ( reminding > 1 ) then
+            m := ( others => '0' );
+            m( m'high downto m'high - reminding + 1 ) := value( reminding - 1 downto 0 );
+        else
+            m := ( others => '0' );
+        end if;
+
+        if (arg = x"00000000") then
+            y := (others => '0');
+        else
+            y := s & std_logic_vector( e ) & std_logic_vector( m );
+        end if;
+
+        return y;
+    end function to_float;
+
+    function to_fixed( arg : std_logic_vector ) return std_logic_vector is
+        variable y : unsigned( 31 downto 0 );
+        variable s : std_logic;
+        variable e : unsigned( 7 downto 0 );
+        variable m_index_max : integer range -127 to 128;
+
+    begin
+        s := arg( 31 );
+        e := unsigned(arg(30 downto 23));
+        m_index_max := to_integer(signed(30-(126-e)));
+
+        if (arg = x"00000000") then
+            y := (others => '0');
+        else
+            y := (others => '0');
+            case m_index_max is
+                when 30 => y(30 downto 7):= '1' & unsigned( arg(22 downto 0) );
+                when 29 => y(29 downto 6):= '1' & unsigned( arg(22 downto 0) );
+                when 28 => y(28 downto 5):= '1' & unsigned( arg(22 downto 0) );
+                when 27 => y(27 downto 4):= '1' & unsigned( arg(22 downto 0) );
+                when 26 => y(26 downto 3):= '1' & unsigned( arg(22 downto 0) );
+                when 25 => y(25 downto 2):= '1' & unsigned( arg(22 downto 0) );
+                when 24 => y(24 downto 1):= '1' & unsigned( arg(22 downto 0) );
+                when 23 => y(23 downto 0):= '1' & unsigned( arg(22 downto 0) );
+                when 22 => y(22 downto 0):= '1' & unsigned( arg(22 downto 1) );
+                when 21 => y(21 downto 0):= '1' & unsigned( arg(22 downto 2) );
+                when 20 => y(20 downto 0):= '1' & unsigned( arg(22 downto 3) );
+                when 19 => y(19 downto 0):= '1' & unsigned( arg(22 downto 4) );
+                when 18 => y(18 downto 0):= '1' & unsigned( arg(22 downto 5) );
+                when 17 => y(17 downto 0):= '1' & unsigned( arg(22 downto 6) );
+                when 16 => y(16 downto 0):= '1' & unsigned( arg(22 downto 7) );
+                when 15 => y(15 downto 0):= '1' & unsigned( arg(22 downto 8) );
+                when 14 => y(14 downto 0):= '1' & unsigned( arg(22 downto 9) );
+                when 13 => y(13 downto 0):= '1' & unsigned( arg(22 downto 10) );
+                when 12 => y(12 downto 0):= '1' & unsigned( arg(22 downto 11) );
+                when 11 => y(11 downto 0):= '1' & unsigned( arg(22 downto 12) );
+                when 10 => y(10 downto 0):= '1' & unsigned( arg(22 downto 13) );
+                when 9 => y(9 downto 0):= '1' & unsigned( arg(22 downto 14) );
+                when 8 => y(8 downto 0):= '1' & unsigned( arg(22 downto 15) );
+                when 7 => y(7 downto 0):= '1' & unsigned( arg(22 downto 16) );
+                when 6 => y(6 downto 0):= '1' & unsigned( arg(22 downto 17) );
+                when 5 => y(5 downto 0):= '1' & unsigned( arg(22 downto 18) );
+                when 4 => y(4 downto 0):= '1' & unsigned( arg(22 downto 19) );
+                when 3 => y(3 downto 0):= '1' & unsigned( arg(22 downto 20) );
+                when 2 => y(2 downto 0):= '1' & unsigned( arg(22 downto 21) );
+                when 1 => y(1 downto 0):= '1' & unsigned( arg(22 downto 22) );
+                when 0 => y(0):= '1';
+                when others => null;
+            end case;
+            if ( s = '1' ) then
+                y := not(y);
+                y:=  y + x"00000001";
+            end if;
+        end if;
+
+        return std_logic_vector( y );
+    end function to_fixed;
+
+end package body float;
diff --git a/float_add.vhd b/test/float_add.vhd
similarity index 100%
rename from float_add.vhd
rename to test/float_add.vhd
diff --git a/test/sine.vhd b/test/sine.vhd
new file mode 100644
index 0000000..876ad42
--- /dev/null
+++ b/test/sine.vhd
@@ -0,0 +1,9 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+library work;
+    use work.test_utility.all;
+
+package sine_data is
+    constant expected : real_array( 0 to 1023 ) := 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+end package sine_data;
+
diff --git a/test/sine_cosine.vhd b/test/sine_cosine.vhd
new file mode 100644
index 0000000..94c7cc8
--- /dev/null
+++ b/test/sine_cosine.vhd
@@ -0,0 +1,9 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+library work;
+    use work.test_utility.all;
+
+package sine_cosine_data is
+    constant expected : real_array( 0 to 1023 ) := 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10393e+00,2.767896e+00,3.198138e+00,3.486855e+00,3.625237e+00,3.610272e+00,3.444852e+00,3.137662e+00,2.702846e+00,2.159460e+00,1.530734e+00,8.431832e-01,1.255811e-01,-5.921449e-01,-1.280068e+00,-1.909413e+00,-2.453665e+00,-2.889591e+00,-3.198138e+00,-3.365158e+00,-3.381965e+00,-3.245665e+00,-2.959269e+00,-2.531583e+00,-1.976869e+00,-1.314300e+00,-5.672265e-01,2.377218e-01,1.071653e+00,1.904529e+00,2.706305e+00,3.448095e+00,4.103275e+00,4.648502e+00,5.064612e+00,5.337355e+00,5.457937e+00,5.423363e+00,5.236545e+00,4.906189e+00,4.446461e+00,3.876442e+00,3.219390e+00,2.501845e+00,1.752613e+00,1.001652e+00,2.789205e-01,-3.867718e-01,-9.688737e-01,-1.444116e+00,-1.793405e+00,-2.002554e+00,-2.062834e+00,-1.971308e+00,-1.730943e+00,-1.350502e+00,-8.441981e-01,-2.311572e-01,4.653198e-01,1.218652e+00,2.000000e+00,2.779374e+00,3.526787e+00,4.213405e+00,4.812656e+00,5.301255e+00,5.660092e+00,5.874974e+00,5.937166e+00,5.843728e+00,5.597631e+00,5.207640e+00,4.687980e+00,4.057790e+00,3.340388e+00,2.562374e+00,1.752613e+00,9.411229e-01,1.579220e-01,-5.681200e-01,-1.210393e+00,-1.745568e+00,-2.154491e+00,-2.422919e+00,-2.542063e+00,-2.508927e+00,-2.326424e+00,-2.003255e+00,-1.553580e+00,-9.964672e-01,-3.551633e-01,3.438057e-01,1.071653e+00,1.798444e+00,2.494241e+00,3.130262e+00,3.679986e+00,4.120174e+00,4.431767e+00,4.600617e+00,4.618034e+00,4.481123e+00,4.192898e+00,3.762165e+00,3.203190e+00,2.535150e+00,1.781400e+00,9.685777e-01,1.255806e-01,-7.175396e-01,-1.530734e+00,-2.285103e+00,-2.954008e+00,-3.514094e+00,-3.946185e+00,-4.236010e+00,-4.374763e+00,-4.359427e+00,-4.192897e+00,-3.883861e+00,-3.446462e+00,-2.899757e+00,-2.266983e+00,-1.574657e+00,-8.515586e-01,-1.276198e-01,5.672264e-01,1.204198e+00,1.756773e+00,2.201711e+00,2.519947e+00,2.697327e+00,2.725152e+00,2.600517e+00,2.326424e+00,1.911665e+00,1.370490e+00,7.220587e-01,-1.029217e-02,-7.999491e-01,-1.618035e+00,-2.434522e+00,-3.219390e+00,-3.943765e+00,-4.581040e+00,-5.107891e+00,-5.505172e+00,-5.758650e+00,-5.859553e+00,-5.804903e+00,-5.597631e+00,-5.246466e+00,-4.765594e+00,-4.174115e+00,-3.495308e+00,-2.755738e+00,-1.984229e+00,-1.210763e+00,-4.653196e-01,2.232679e-01,8.284271e-01,1.326865e+00,1.699465e+00,1.932017e+00,2.015770e+00,1.947764e+00,1.730944e+00,1.374045e+00,8.912609e-01,3.016934e-01,-3.713790e-01,-1.101400e+00,-1.859553e+00,-2.615870e+00,-3.340388e+00,-4.004294e+00,-4.581040e+00,-5.047362e+00,-5.384174e+00,-5.577302e+00,-5.618033e+00,-5.503450e+00,-5.236544e+00,-4.826100e+00,-4.286365e+00,-3.636495e+00,-2.899828e+00,-2.102985e+00,-1.274848e+00,-4.454529e-01,3.551632e-01,1.098114e+00,1.756774e+00,2.307796e+00,2.732011e+00,3.015160e+00,3.148441e+00,3.128845e+00,2.959269e+00,2.648403e+00,2.210393e+00,1.664299e+00,1.033354e+00,3.440749e-01,-3.747628e-01,-1.093230e+00,-1.781400e+00,-2.410498e+00,-2.954008e+00,-3.388699e+00,-3.695518e+00,-3.860319e+00,-3.874418e+00,-3.734925e+00,-3.444852e+00,-3.013011e+00,-2.453665e+00,-1.785994e+00,-1.033353e+00,-2.223782e-01,6.180345e-01,1.457838e+00,2.266983e+00,3.016577e+00,3.679986e+00,4.233859e+00,4.659025e+00,4.941224e+00,5.071653e+00,5.047308e+00,4.871089e+00,4.551693e+00,4.103275e+00,3.544904e+00,2.899828e+00,2.194575e+00,1.457937e+00,7.198612e-01,1.029289e-02,-6.419711e-01,-1.210393e+00,-1.671717e+00,-2.006862e+00,-2.201657e+00,-2.247386e+00,-2.141128e+00,-1.885864e+00,-1.490369e+00,-9.688745e-01,-3.405195e-01,3.713791e-01,1.140226e+00,1.937166e+00,2.732195e+00,3.495308e+00,4.197658e+00,4.812656e+00,5.317002e+00,5.691571e+00,5.922154e+00,6.000000e+00,5.922154e+00,5.691572e+00,5.317002e+00,4.812656e+00,4.197658e+00,3.495308e+00,2.732195e+00,1.937166e+00,1.140226e+00,3.713793e-01,-3.405197e-01,-9.688740e-01,-1.490369e+00,-1.885864e+00,-2.141128e+00,-2.247387e+00,-2.201657e+00,-2.006862e+00,-1.671718e+00,-1.210394e+00,-6.419711e-01,1.029277e-02,7.198613e-01);
+end package sine_cosine_data;
+
diff --git a/test/tb_fsm_add.vhd b/test/tb_fsm_add.vhd
new file mode 100644
index 0000000..ee56e22
--- /dev/null
+++ b/test/tb_fsm_add.vhd
@@ -0,0 +1,115 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.float_pkg.all;
+
+library work;
+    use work.test_utility.all;
+    use work.sine_data.all;
+    use work.cosine_data.all;
+    use work.sine_cosine_data.all;
+
+library std;
+    use std.env.all;
+    use std.textio.all;
+
+entity tb_fsm_add is
+    generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := true );
+end;
+
+architecture test of tb_fsm_add is
+    signal clk               : std_logic := '0';
+    signal reset             : std_logic := '1';
+    signal run_calc          : std_logic;
+    signal calc_cnt          : std_logic_vector( 3 downto 0 );
+
+    signal signal_a_read     : std_logic;
+    signal signal_a_readdata : std_logic_vector( 31 downto 0 );
+
+    signal signal_b_read     : std_logic;
+    signal signal_b_readdata : std_logic_vector( 31 downto 0 );
+
+    signal signal_write      : std_logic;
+    signal signal_writedata  : std_logic_vector( 31 downto 0 );
+
+begin
+
+    u_fsm_add : entity work.fsm_add
+        port map (
+             clk               => clk,
+             reset             => reset,
+             run_calc          => run_calc,
+             calc_cnt          => calc_cnt,
+
+             signal_a_read     => signal_a_read,
+             signal_a_readdata => signal_a_readdata,
+
+             signal_b_read     => signal_b_read,
+             signal_b_readdata => signal_b_readdata,
+
+             signal_write      => signal_write,
+             signal_writedata  => signal_writedata
+         );
+
+    a_clk: clk <= not clk after 10 ns;
+
+    a_reset: process( clk )
+    begin
+        if falling_edge( clk ) then
+            reset <= '0';
+        end if;
+    end process;
+
+    input_data_a_simulus: process is
+        variable index : integer := 0;
+    begin
+        while true loop
+            signal_a_readdata <= to_std_logic_vector( to_float( work.sine_data.expected( index ) ) );
+            wait until rising_edge( signal_a_read );
+            if ( index < 1023 ) then
+                index := index + 1;
+            end if;
+        end loop;
+    end process input_data_a_simulus;
+
+    input_data_b_simulus: process is
+        variable index : integer := 0;
+    begin
+        while true loop
+            signal_b_readdata <= to_std_logic_vector( to_float( work.cosine_data.expected( index ) ) );
+            wait until rising_edge( signal_b_read );
+            if ( index < 1023 ) then
+                index := index + 1;
+            end if;
+        end loop;
+    end process input_data_b_simulus;
+
+    stimulus: process is
+        variable expected : real;
+        variable float_value : float32;
+        variable real_value : real;
+        variable abs_err : real := 0.5e-1;
+    begin
+        std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );
+        std.textio.write( std.textio.OUTPUT, "Starting tb_fsm_add" & LF );
+        wait until falling_edge( reset );
+
+        wait until falling_edge( clk );
+        run_calc <= '1';
+        wait until falling_edge( clk );
+
+        for i in 0 to 16 loop
+            wait until rising_edge( signal_write );
+            expected := work.sine_cosine_data.expected( i + 1 );
+            float_value := to_float( signal_writedata );
+            real_value := to_real( float_value );
+            assert_near( real_value, expected, abs_err );
+        end loop;
+
+        if GUI_MODE = true then
+            finish;
+        else
+            stop;
+        end if;
+    end process stimulus;
+
+end architecture test;
diff --git a/test/tb_fsm_add.wave b/test/tb_fsm_add.wave
new file mode 100644
index 0000000..8f05289
--- /dev/null
+++ b/test/tb_fsm_add.wave
@@ -0,0 +1,3 @@
+$ version 1.1
+/tb_fsm_add/*
+/tb_fsm_add/u_fsm_add/*
diff --git a/test/tb_top_entity_float_add.vhd b/test/tb_top_entity_float_add.vhd
deleted file mode 100644
index 23d0067..0000000
--- a/test/tb_top_entity_float_add.vhd
+++ /dev/null
@@ -1,85 +0,0 @@
-library ieee;
-    use ieee.std_logic_1164.all;
-
-library std;
-    use std.env.all;
-
-library work;
-    use work.test_utility.all;
-
-entity tb_top_entity_float_add is
-    generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := true );
-end;
-
-architecture test of tb_top_entity_float_add is
-    signal clk           : std_logic := '0';
-    signal reset         : std_logic := '1';
-    signal run_calc      : std_logic := '0';
-    signal operand_a     : std_logic_vector(31 downto 0) := ( others => '0' );
-    signal operand_b     : std_logic_vector(31 downto 0) := ( others => '0' );
-    signal result        : std_logic_vector(31 downto 0);
-    signal calc_complete : std_logic;
-begin
-
-    u_top_entity_float_add : entity work.top_entity_float_add
-        port map (
-            clk           => clk,
-            reset         => reset,
-            run_calc      => run_calc,
-            operand_a     => operand_a,
-            operand_b     => operand_b,
-            result        => result,
-            calc_complete => calc_complete
-        );
-
-    a_clk: clk <= not clk after 10 ns;
-
-    a_reset: process( clk )
-    begin
-        if falling_edge( clk ) then
-            reset <= '0';
-        end if;
-    end process;
-
-    delay : process
-        variable res      : std_logic_vector( 31 downto 0 );
-        variable expected : std_logic_vector( 31 downto 0 );
-    begin
-
-        wait until falling_edge( reset );
-
-        -----------------------------------------------------------------------
-        wait until rising_edge( clk );
-        run_calc      <= '1';
-        operand_a     <= x"01000000";
-        operand_b     <= x"02000000";
-        wait until rising_edge( calc_complete );
-        run_calc      <= '0';
-        if ( CHECK_RESULTS ) then
-            res  := result;
-            expected := x"02200000";
-            assert_eq( res, expected );
-        end if;
-        wait until rising_edge( clk );
-
-        -----------------------------------------------------------------------
-        wait until rising_edge( clk );
-        run_calc      <= '1';
-        operand_a     <= x"4048f5c3"; -- 3.14
-        operand_b     <= x"402d70a4"; -- 2.71
-        wait until rising_edge( calc_complete );
-        if ( CHECK_RESULTS ) then
-            res  := result;
-            expected := x"40bb3333"; -- 5.85
-            assert_eq( res, expected );
-        end if;
-        wait until rising_edge( clk );
-
-        if GUI_MODE = true then
-            finish;
-        else
-            stop;
-        end if;
-    end process delay;
-
-end architecture test;
diff --git a/top_entity_float_add.vhd b/top_entity_float_add.vhd
deleted file mode 100644
index aa583c7..0000000
--- a/top_entity_float_add.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;     -- Bibliothek für std_logic und std_logic_vector
-use IEEE.NUMERIC_STD.ALL;        -- Bibliothek für signed und unsigned Datentypen
-
-entity top_entity_float_add is
-    port (
-             clk   : in std_logic;                         -- Eingangssignal Systemtakt
-             reset : in std_logic;                         -- Eingangssignal Reset zum Setzen der Default Werte
-             run_calc: in std_logic;                       -- Eingangssignal wenn aktiv soll gerechnet werden
-             operand_a : in STD_LOGIC_VECTOR(31 downto 0); -- Erster Operand in 32-bit float
-             operand_b : in STD_LOGIC_VECTOR(31 downto 0); -- Zweiter Operand in 32-bit float
-             result : out std_logic_vector(31 downto 0);   -- Endergebnis Berechnung Addition (im slv ist ein 32-bit float gespeichert)
-             calc_complete : out std_logic                 -- Flag das anzeiugt wann die Berechnung fertig ist (bei 1=high)
-         );
-end top_entity_float_add;
-
-architecture Behavioral of top_entity_float_add is
-
-    -- Legen Sie ein signal result_sum als std_logic_vector mit Laenge 32 Bit an
-
-    -- Legen Sie ein signal start als std_logic
-
-    -- Legen Sie ein signal done als std_logic
-
-begin
-
-    -- Instanziieren Sie direkt die float_add Komponente
-    -- Als Takt und Reset sollen die jeweiligen Eingaenge der top_entity_float_add uebergeben werden
-    -- An den anderen Ports die jeweiligen zugehoerigen Signale (welche oben angelegt worden sind)
-    u_float_add : entity work.float_add
-    port map(
-            -- Eingangssignal fuer den Takt
-                clk => ,
-            -- Eingangssignal zum Zuruecksetzen des Zaehlers
-                reset => ,
-            -- Eingang um die Berechnung zu starten
-                start => ,
-            -- Ausgang der anzeigt, dass die Berechnung fertig ist
-                done => ,
-            -- floating point operand a
-                A => ,
-            -- floating point operand b
-                B => ,
-            -- Ergebnis der Addition in floating point
-                sum =>
-                );
-
-      -- Realisieren Sie einen getakteten Prozess control mit folgenden Verhalten
-      --
-      -- Initialisierung der Signale bei Reset aktiv (reset=1):
-      --   result soll=0 sein
-      --   start soll=0 sein
-      --   calc_complete soll=0 sein
-      --
-      -- bei steigende Flanke:
-      --   Nur wenn run_calc gleich 1 ist:
-      --     dann soll wenn done=1 und start=1 ist
-      --       start=0, calc_complete=1 und result_sum dem Ausgang result zugewiesen werden
-      --     ansonsten soll
-      --        start=1, calc_complete=0 sein
-      --
-    control : process(reset,clk)
-    begin
-
-    end process control;
-
-end Behavioral;