Add the first version of the exercise with test bench

scripts/check_test_results.sh

@@ -0,0 +1,15 @@
+#!/bin/bash
+script_dir=$(cd $(dirname "${BASH_SOURCE[0]}") && pwd)
+
+if [ $# -ne 1 ]
+then
+    echo Usage $0 test-output-file
+    exit 1
+fi
+
+cat $1 | sed -z -e 's/\(py_.* \[\)/ \[/g' | ${script_dir}/highlight_test_results.sh
+
+if grep -q FAIL $1
+then
+    exit 1
+fi

scripts/execute_and_highlight.sh

@@ -0,0 +1,14 @@
+#!/bin/bash
+script_path="$( dirname  "$( readlink -f "${BASH_SOURCE[0]}" )" )"
+
+if [ $# -lt 1 ]
+then
+    echo " usage: execute_and_highlight command arguments"
+    exit 1
+fi
+
+cmd=$1
+shift 1
+$cmd $@ | $script_path/highlight_test_results.sh
+test ${PIPESTATUS[0]} -eq 0
+

scripts/ghdl.mk

@@ -0,0 +1,65 @@
+#
+#
+#
+#
+
+# Make sure that the top level is assigned to main
+$(if $(main),,\
+$(error Assign top level entity name to variable "main"))
+
+# Make sure that at least on vhdl source is assigned
+$(if $(vhdl_srcs),,\
+$(error Assign at least on vhdl source to variable "vhdl_srcs"))
+
+# Append prefix -d to all generics
+generics  = $(addprefix -g,$(generics))
+
+# Add VHDL 2008 as default build standard
+vhdl_flags += --std=08
+vhdl_flags += -frelaxed-rules
+#vhdl_flags += --ieee-asserts=disable-at-0
+
+vhdl_objs = $(vhdl_srcs:.vhd=.o)
+
+assert_level := error
+
+.PHONY: sim clean
+
+sim: ${main}
+	@scripts/execute_and_highlight.sh \
+		ghdl \
+		-r ${vhdl_flags} ${main} \
+		--ieee-asserts=disable-at-0 \
+		-gCHECK_RESULTS=${CHECK_RESULTS} \
+		--read-wave-opt=test/${main}.wave \
+		--assert-level=${assert_level}
+
+gui: test/${main}.ghw
+	@echo "Viewing $<"
+	@gtkwave $< --script=test/gtkwave.view
+
+test/${main}.ghw: ${main} test/${main}.wave
+	@ghdl -r ${vhdl_flags} ${main} \
+		--read-wave-opt=test/${main}.wave \
+		--wave=$@
+
+${main}: $(vhdl_objs)
+	@echo "Elaborating ${main}"
+	@ghdl -e ${vhdl_flags} ${main}
+
+%.o: %.vhd
+	@echo "Analysing $<"
+	@ghdl -a ${vhdl_flags} $<
+
+clean:
+	@ghdl --clean
+	@rm -rf ${main}.ghw work-obj08.cf ${vhdl_objs} ${main} ${artifacts}
+
+help:
+	@echo Use ghdl to simulate and synthesis a vhdl design.
+	@echo
+	@echo Build configuration variables:
+	@echo 	main        main entity
+	@echo 	vhdl_flags
+	@echo 	generics
+

scripts/highlight_test_results.sh

@@ -0,0 +1,7 @@
+#!/bin/bash
+
+red=$(tput setaf 1)
+green=$(tput setaf 2)
+default=$(tput sgr0)
+
+sed "s/FAIL/${red}FAIL${default}/" | sed "s/OK/${green}OK${default}/"

scripts/questa-sim.mk

@@ -0,0 +1,63 @@
+#
+#
+#
+#
+
+# Make sure that the top level is assigned to main
+$(if $(main),,\
+$(error Assign top level entity name to variable "main"))
+
+# Make sure that at least on vhdl source is assigned
+$(if $(vhdl_srcs),,\
+$(error Assign at least on vhdl source to variable "vhdl_srcs"))
+
+# Append prefix -d to all generics
+generics  = $(addprefix -g,$(generics))
+
+# Add VHDL 2008 as default build standard
+vhdl_flags += -2008
+
+vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
+verilog_objs = $(verilog_srcs:.v=.vo)
+
+assert_level := error
+
+.PHONY: sim clean
+
+sim: ${verilog_objs} ${vhdl_objs}
+	@vsim -voptargs=+acc -c work.${main} -g CHECK_RESULTS=true -do "run -all" \
+	 | scripts/highlight_test_results.sh
+
+gui: ${verilog_objs} ${vhdl_objs}
+	@vsim -voptargs=+acc work.${main} -g CHECK_RESULTS=false -do "do test/vsim.wave; run -all"
+
+%.vo: %.v .libwork
+	@echo "Analysing $<"
+	@vlog -work work ${verilog_flags} $<
+
+%.vhdo: %.vhd .libwork
+	@echo "Analysing $<"
+	@vcom -work work ${vhdl_flags} $<
+
+
+.libwork:
+	@vlib work && vmap work work && touch $@
+
+clean:
+	@rm -rf work \
+	 .libwork \
+	 transcript \
+	 modelsim.ini \
+	 vlog.opt \
+	 vsim.wlf \
+	 data.py \
+	 data.pyc \
+
+help:
+	@echo Use ghdl to simulate and synthesis a vhdl design.
+	@echo
+	@echo Build configuration variables:
+	@echo 	main        main entity
+	@echo 	vhdl_flags
+	@echo 	generics
+

scripts/vhdl.mk

@@ -0,0 +1,23 @@
+
+ghdl_version = $(shell ghdl --version 2> /dev/null)
+vsim_version = $(shell vsim -version 2> /dev/null)
+
+# in case verilog is part of the build a verilog capable simulator is required
+ifdef verilog_srcs
+ifneq (${vsim_version},)
+include scripts/questa-sim.mk
+else
+$(error No HDL simulation tool found for verilog!)
+endif
+else
+ifneq (${vsim_version},)
+include scripts/questa-sim.mk
+else
+ifneq (${ghdl_version},)
+include scripts/ghdl.mk
+else
+$(error No HDL simulation tool found!)
+endif
+endif
+endif
+