116 lines
3.4 KiB
VHDL
116 lines
3.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.float_pkg.all;
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library work;
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use work.test_utility.all;
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use work.sine_data.all;
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use work.cosine_data.all;
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use work.sine_cosine_data.all;
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library std;
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use std.env.all;
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use std.textio.all;
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entity tb_fsm_add is
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generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := true );
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end;
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architecture test of tb_fsm_add is
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal run_calc : std_logic;
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signal calc_cnt : std_logic_vector( 3 downto 0 );
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signal signal_a_read : std_logic;
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signal signal_a_readdata : std_logic_vector( 31 downto 0 );
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signal signal_b_read : std_logic;
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signal signal_b_readdata : std_logic_vector( 31 downto 0 );
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signal signal_write : std_logic;
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signal signal_writedata : std_logic_vector( 31 downto 0 );
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begin
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u_fsm_add : entity work.fsm_add
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port map (
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clk => clk,
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reset => reset,
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run_calc => run_calc,
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calc_cnt => calc_cnt,
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signal_a_read => signal_a_read,
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signal_a_readdata => signal_a_readdata,
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signal_b_read => signal_b_read,
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signal_b_readdata => signal_b_readdata,
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signal_write => signal_write,
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signal_writedata => signal_writedata
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);
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a_clk: clk <= not clk after 10 ns;
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a_reset: process( clk )
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begin
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if falling_edge( clk ) then
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reset <= '0';
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end if;
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end process;
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input_data_a_simulus: process is
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variable index : integer := 0;
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begin
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while true loop
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signal_a_readdata <= to_std_logic_vector( to_float( work.sine_data.expected( index ) ) );
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wait until rising_edge( signal_a_read );
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if ( index < 1023 ) then
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index := index + 1;
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end if;
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end loop;
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end process input_data_a_simulus;
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input_data_b_simulus: process is
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variable index : integer := 0;
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begin
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while true loop
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signal_b_readdata <= to_std_logic_vector( to_float( work.cosine_data.expected( index ) ) );
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wait until rising_edge( signal_b_read );
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if ( index < 1023 ) then
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index := index + 1;
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end if;
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end loop;
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end process input_data_b_simulus;
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stimulus: process is
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variable expected : real;
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variable float_value : float32;
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variable real_value : real;
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variable abs_err : real := 0.5e-1;
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begin
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std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );
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std.textio.write( std.textio.OUTPUT, "Starting tb_fsm_add" & LF );
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wait until falling_edge( reset );
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wait until falling_edge( clk );
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run_calc <= '1';
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wait until falling_edge( clk );
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for i in 0 to 16 loop
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wait until rising_edge( signal_write );
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expected := work.sine_cosine_data.expected( i + 1 );
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float_value := to_float( signal_writedata );
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real_value := to_real( float_value );
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assert_near( real_value, expected, abs_err );
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end loop;
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if GUI_MODE = true then
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finish;
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else
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stop;
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end if;
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end process stimulus;
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end architecture test;
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