86 lines
2.5 KiB
VHDL
86 lines
2.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library std;
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use std.env.all;
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library work;
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use work.test_utility.all;
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entity tb_top_entity_float_add is
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generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := true );
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end;
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architecture test of tb_top_entity_float_add is
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal run_calc : std_logic := '0';
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signal operand_a : std_logic_vector(31 downto 0) := ( others => '0' );
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signal operand_b : std_logic_vector(31 downto 0) := ( others => '0' );
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signal result : std_logic_vector(31 downto 0);
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signal calc_complete : std_logic;
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begin
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u_top_entity_float_add : entity work.top_entity_float_add
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port map (
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clk => clk,
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reset => reset,
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run_calc => run_calc,
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operand_a => operand_a,
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operand_b => operand_b,
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result => result,
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calc_complete => calc_complete
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);
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a_clk: clk <= not clk after 10 ns;
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a_reset: process( clk )
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begin
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if falling_edge( clk ) then
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reset <= '0';
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end if;
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end process;
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delay : process
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variable res : std_logic_vector( 31 downto 0 );
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variable expected : std_logic_vector( 31 downto 0 );
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begin
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wait until falling_edge( reset );
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-----------------------------------------------------------------------
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wait until rising_edge( clk );
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run_calc <= '1';
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operand_a <= x"01000000";
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operand_b <= x"02000000";
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wait until rising_edge( calc_complete );
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run_calc <= '0';
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if ( CHECK_RESULTS ) then
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res := result;
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expected := x"02200000";
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assert_eq( res, expected );
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end if;
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wait until rising_edge( clk );
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-----------------------------------------------------------------------
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wait until rising_edge( clk );
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run_calc <= '1';
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operand_a <= x"4048f5c3"; -- 3.14
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operand_b <= x"402d70a4"; -- 2.71
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wait until rising_edge( calc_complete );
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if ( CHECK_RESULTS ) then
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res := result;
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expected := x"40bb3333"; -- 5.85
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assert_eq( res, expected );
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end if;
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wait until rising_edge( clk );
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if GUI_MODE = true then
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finish;
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else
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stop;
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end if;
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end process delay;
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end architecture test;
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