signal_processing_vorlage/tests/hardware/vhdl.mk

ghdl_version = $(shell ghdl --version 2> /dev/null)
vsim_version = $(shell vsim -version 2> /dev/null)

# in case verilog is part of the build a verilog capable simulator is required
ifdef verilog_srcs
ifneq (${vsim_version},)
include ../questa-sim.mk
else
$(error No HDL simulation tool found for verilog!)
endif
else
ifneq (${vsim_version},)
include ../questa-sim.mk
else
ifneq (${ghdl_version},)
include ../ghdl.mk
else
$(error No HDL simulation tool found!)
endif
endif
endif