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Johannes Kutning
2023-10-31 07:47:27 +01:00
commit 0d1b73e3e0
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hardware/signal_processing/add.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.task.all;
entity add is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
signal_a_read : out std_logic;
signal_a_readdata : in std_logic_vector( 31 downto 0 );
signal_b_read : out std_logic;
signal_b_readdata : in std_logic_vector( 31 downto 0 );
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity add;
architecture rtl of add is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
hardware/signal_processing/crc.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.task.all;
entity crc is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
signal_read : out std_logic;
signal_readdata : in std_logic_vector( 31 downto 0 );
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity crc;
architecture rtl of crc is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
hardware/signal_processing/fft.vhd
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------------------------------------------------------------------------
-- fft
--
-- calculation of FFT magnitude
--
-- Inputs:
-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
--
-- Outputs
-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
--
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.task.all;
use work.float.all;
entity fft is
generic (
-- input data width of real/img part
input_data_width : integer := 32;
-- output data width of real/img part
output_data_width : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
signal_read : out std_logic;
signal_readdata : in std_logic_vector( 31 downto 0 );
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity fft;
architecture rtl of fft is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
hardware/signal_processing/rand.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.task.all;
entity rand is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
seed : in work.reg32.word;
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity rand;
architecture rtl of rand is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
hardware/signal_processing/signal_processing.vhd
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--! Use ieee library for std_logic types.
library ieee;
use ieee.std_logic_1164.all;
--! Use the niosII library for all processor system components
library niosII;
--! Use the pll_200 library for the PLL 200 MHz clock generation
library pll_main;
entity signal_processing is
port
(
clk_input : in std_logic;
reset_n : in std_logic;
--! Push button key_0 used to start a single execution of the signal
--! processing.
key_start : in std_logic;
leds : out std_logic_vector( 7 downto 0 )
);
end entity signal_processing;
architecture struct of signal_processing is
--! input clock synchronous reset
signal sync_reset : std_logic;
--! main clock for the NiosII system
signal clk_main : std_logic;
--! main clock from PLL is locked and the system reset can be released.
signal locked_main : std_logic;
--! main clock synchronous reset
signal sync_reset_main : std_logic;
signal sync_reset_main_n : std_logic;
signal sw_leds : std_logic_vector( 7 downto 0 );
signal hw_leds : std_logic_vector( 7 downto 0 );
signal hardware_task_0_address : std_logic_vector(3 downto 0);
signal hardware_task_0_read : std_logic;
signal hardware_task_0_readdata : std_logic_vector(31 downto 0);
signal hardware_task_0_write : std_logic;
signal hardware_task_0_writedata : std_logic_vector(31 downto 0);
signal hardware_task_1_address : std_logic_vector(3 downto 0);
signal hardware_task_1_read : std_logic;
signal hardware_task_1_readdata : std_logic_vector(31 downto 0);
signal hardware_task_1_write : std_logic;
signal hardware_task_1_writedata : std_logic_vector(31 downto 0);
signal hardware_task_2_address : std_logic_vector(3 downto 0);
signal hardware_task_2_read : std_logic;
signal hardware_task_2_readdata : std_logic_vector(31 downto 0);
signal hardware_task_2_write : std_logic;
signal hardware_task_2_writedata : std_logic_vector(31 downto 0);
signal hardware_task_3_address : std_logic_vector(3 downto 0);
signal hardware_task_3_read : std_logic;
signal hardware_task_3_readdata : std_logic_vector(31 downto 0);
signal hardware_task_3_write : std_logic;
signal hardware_task_3_writedata : std_logic_vector(31 downto 0);
signal hardware_task_4_address : std_logic_vector(3 downto 0);
signal hardware_task_4_read : std_logic;
signal hardware_task_4_readdata : std_logic_vector(31 downto 0);
signal hardware_task_4_write : std_logic;
signal hardware_task_4_writedata : std_logic_vector(31 downto 0);
signal hardware_task_5_address : std_logic_vector(3 downto 0);
signal hardware_task_5_read : std_logic;
signal hardware_task_5_readdata : std_logic_vector(31 downto 0);
signal hardware_task_5_write : std_logic;
signal hardware_task_5_writedata : std_logic_vector(31 downto 0);
signal hardware_task_6_address : std_logic_vector(3 downto 0);
signal hardware_task_6_read : std_logic;
signal hardware_task_6_readdata : std_logic_vector(31 downto 0);
signal hardware_task_6_write : std_logic;
signal hardware_task_6_writedata : std_logic_vector(31 downto 0);
signal data_channel_0_hw_sink_write : std_logic;
signal data_channel_0_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_0_hw_source_read : std_logic;
signal data_channel_0_hw_source_readdata : std_logic_vector(31 downto 0);
signal data_channel_1_hw_sink_write : std_logic;
signal data_channel_1_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_1_hw_source_read : std_logic;
signal data_channel_1_hw_source_readdata : std_logic_vector(31 downto 0);
signal data_channel_2_hw_sink_write : std_logic;
signal data_channel_2_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_2_hw_source_read : std_logic;
signal data_channel_2_hw_source_readdata : std_logic_vector(31 downto 0);
signal data_channel_3_hw_sink_write : std_logic;
signal data_channel_3_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_3_hw_source_read : std_logic;
signal data_channel_3_hw_source_readdata : std_logic_vector(31 downto 0);
signal data_channel_4_hw_sink_write : std_logic;
signal data_channel_4_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_4_hw_source_read : std_logic;
signal data_channel_4_hw_source_readdata : std_logic_vector(31 downto 0);
signal data_channel_5_hw_sink_write : std_logic;
signal data_channel_5_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_5_hw_source_read : std_logic;
signal data_channel_5_hw_source_readdata : std_logic_vector(31 downto 0);
signal data_channel_6_hw_sink_write : std_logic;
signal data_channel_6_hw_sink_writedata : std_logic_vector(31 downto 0);
signal data_channel_6_hw_source_read : std_logic;
signal data_channel_6_hw_source_readdata : std_logic_vector(31 downto 0);
begin
-- Synchronize the external reset to the external clock domain
u_sync_rst_50: entity work.sync_rst
port map
(
clk => clk_input,
reset => not reset_n,
rst_sync => sync_reset
);
-- PLL for the main system clock
u_pll_main: entity pll_main.pll_main
port map
(
refclk => clk_input, -- in std_logic
rst => sync_reset, -- in std_logic
outclk_0 => clk_main, -- out std_logic
locked => locked_main -- out std_logic
);
-- Synchronize the main reset to the main clock domain
u_sync_rst_main: entity work.sync_rst
port map
(
clk => clk_main,
reset => not locked_main and sync_reset,
rst_sync => sync_reset_main
);
sync_reset_main_n <= not sync_reset_main;
-- NiosII system
u_niosII : entity niosii.niosII
port map
(
clk_clk => clk_main,
reset_reset_n => sync_reset_main_n,
key_start_export => key_start,
leds_export => sw_leds,
data_channel_0_hw_sink_write => data_channel_0_hw_sink_write,
data_channel_0_hw_sink_writedata => data_channel_0_hw_sink_writedata,
data_channel_0_hw_source_read => data_channel_0_hw_source_read,
data_channel_0_hw_source_readdata => data_channel_0_hw_source_readdata,
data_channel_1_hw_sink_write => data_channel_1_hw_sink_write,
data_channel_1_hw_sink_writedata => data_channel_1_hw_sink_writedata,
data_channel_1_hw_source_read => data_channel_1_hw_source_read,
data_channel_1_hw_source_readdata => data_channel_1_hw_source_readdata,
data_channel_2_hw_sink_write => data_channel_2_hw_sink_write,
data_channel_2_hw_sink_writedata => data_channel_2_hw_sink_writedata,
data_channel_2_hw_source_read => data_channel_2_hw_source_read,
data_channel_2_hw_source_readdata => data_channel_2_hw_source_readdata,
data_channel_3_hw_sink_write => data_channel_3_hw_sink_write,
data_channel_3_hw_sink_writedata => data_channel_3_hw_sink_writedata,
data_channel_3_hw_source_read => data_channel_3_hw_source_read,
data_channel_3_hw_source_readdata => data_channel_3_hw_source_readdata,
data_channel_4_hw_sink_write => data_channel_4_hw_sink_write,
data_channel_4_hw_sink_writedata => data_channel_4_hw_sink_writedata,
data_channel_4_hw_source_read => data_channel_4_hw_source_read,
data_channel_4_hw_source_readdata => data_channel_4_hw_source_readdata,
data_channel_5_hw_sink_write => data_channel_5_hw_sink_write,
data_channel_5_hw_sink_writedata => data_channel_5_hw_sink_writedata,
data_channel_5_hw_source_read => data_channel_5_hw_source_read,
data_channel_5_hw_source_readdata => data_channel_5_hw_source_readdata,
data_channel_6_hw_sink_write => data_channel_6_hw_sink_write,
data_channel_6_hw_sink_writedata => data_channel_6_hw_sink_writedata,
data_channel_6_hw_source_read => data_channel_6_hw_source_read,
data_channel_6_hw_source_readdata => data_channel_6_hw_source_readdata,
hardware_task_0_task_address => hardware_task_0_address,
hardware_task_0_task_read => hardware_task_0_read,
hardware_task_0_task_readdata => hardware_task_0_readdata,
hardware_task_0_task_write => hardware_task_0_write,
hardware_task_0_task_writedata => hardware_task_0_writedata,
hardware_task_1_task_address => hardware_task_1_address,
hardware_task_1_task_read => hardware_task_1_read,
hardware_task_1_task_readdata => hardware_task_1_readdata,
hardware_task_1_task_write => hardware_task_1_write,
hardware_task_1_task_writedata => hardware_task_1_writedata,
hardware_task_2_task_address => hardware_task_2_address,
hardware_task_2_task_read => hardware_task_2_read,
hardware_task_2_task_readdata => hardware_task_2_readdata,
hardware_task_2_task_write => hardware_task_2_write,
hardware_task_2_task_writedata => hardware_task_2_writedata,
hardware_task_3_task_address => hardware_task_3_address,
hardware_task_3_task_read => hardware_task_3_read,
hardware_task_3_task_readdata => hardware_task_3_readdata,
hardware_task_3_task_write => hardware_task_3_write,
hardware_task_3_task_writedata => hardware_task_3_writedata,
hardware_task_4_task_address => hardware_task_4_address,
hardware_task_4_task_read => hardware_task_4_read,
hardware_task_4_task_readdata => hardware_task_4_readdata,
hardware_task_4_task_write => hardware_task_4_write,
hardware_task_4_task_writedata => hardware_task_4_writedata,
hardware_task_5_task_address => hardware_task_5_address,
hardware_task_5_task_read => hardware_task_5_read,
hardware_task_5_task_readdata => hardware_task_5_readdata,
hardware_task_5_task_write => hardware_task_5_write,
hardware_task_5_task_writedata => hardware_task_5_writedata,
hardware_task_6_task_address => hardware_task_6_address,
hardware_task_6_task_read => hardware_task_6_read,
hardware_task_6_task_readdata => hardware_task_6_readdata,
hardware_task_6_task_write => hardware_task_6_write,
hardware_task_6_task_writedata => hardware_task_6_writedata
);
u_task_sine: entity work.task_sine
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_0_address,
read => hardware_task_0_read,
readdata => hardware_task_0_readdata,
write => hardware_task_0_write,
writedata => hardware_task_0_writedata,
signal_write => data_channel_0_hw_sink_write ,
signal_writedata => data_channel_0_hw_sink_writedata
);
u_task_cosine: entity work.task_sine
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_1_address,
read => hardware_task_1_read,
readdata => hardware_task_1_readdata,
write => hardware_task_1_write,
writedata => hardware_task_1_writedata,
signal_write => data_channel_1_hw_sink_write ,
signal_writedata => data_channel_1_hw_sink_writedata
);
u_task_rand: entity work.task_rand
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_2_address,
read => hardware_task_2_read,
readdata => hardware_task_2_readdata,
write => hardware_task_2_write,
writedata => hardware_task_2_writedata,
signal_write => data_channel_2_hw_sink_write ,
signal_writedata => data_channel_2_hw_sink_writedata
);
u_task_add_sine_cosine: entity work.task_add
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_3_address,
read => hardware_task_3_read,
readdata => hardware_task_3_readdata,
write => hardware_task_3_write,
writedata => hardware_task_3_writedata,
signal_a_read => data_channel_0_hw_source_read,
signal_a_readdata => data_channel_0_hw_source_readdata,
signal_b_read => data_channel_1_hw_source_read,
signal_b_readdata => data_channel_1_hw_source_readdata,
signal_write => data_channel_3_hw_sink_write ,
signal_writedata => data_channel_3_hw_sink_writedata
);
u_task_add_rand: entity work.task_add
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_4_address,
read => hardware_task_4_read,
readdata => hardware_task_4_readdata,
write => hardware_task_4_write,
writedata => hardware_task_4_writedata,
signal_a_read => data_channel_2_hw_source_read,
signal_a_readdata => data_channel_2_hw_source_readdata,
signal_b_read => data_channel_3_hw_source_read,
signal_b_readdata => data_channel_3_hw_source_readdata,
signal_write => data_channel_4_hw_sink_write ,
signal_writedata => data_channel_4_hw_sink_writedata
);
u_task_fft: entity work.task_fft
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_5_address,
read => hardware_task_5_read,
readdata => hardware_task_5_readdata,
write => hardware_task_5_write,
writedata => hardware_task_5_writedata,
signal_read => data_channel_4_hw_source_read,
signal_readdata => data_channel_4_hw_source_readdata,
signal_write => data_channel_5_hw_sink_write ,
signal_writedata => data_channel_5_hw_sink_writedata
);
u_task_crc: entity work.task_crc
port map (
clk => clk_main,
reset => sync_reset_main,
address => hardware_task_6_address,
read => hardware_task_6_read,
readdata => hardware_task_6_readdata,
write => hardware_task_6_write,
writedata => hardware_task_6_writedata,
signal_read => data_channel_5_hw_source_read,
signal_readdata => data_channel_5_hw_source_readdata,
signal_write => data_channel_6_hw_sink_write ,
signal_writedata => data_channel_6_hw_sink_writedata
);
hw_leds <= ( 0 => reset_n, 1 => sync_reset, 2 => locked_main, 3 => sync_reset_main, others => '0' );
leds <= sw_leds or hw_leds;
end architecture struct;
hardware/signal_processing/sine.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.float.all;
use work.task.all;
entity sine is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
step_size : in work.reg32.word;
phase : in work.reg32.word;
amplitude : in work.reg32.word;
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
);
end entity sine;
architecture rtl of sine is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;