signal_processing_vorlage/hardware/system/pll/pll_main.ppf

<?xml version="1.0" encoding="UTF-8"?>
<pinplan
 variation_name="pll_main"
 megafunction_name="ALTERA_PLL"
 intended_family="Cyclone V"
 specifies="all_ports">
 <global>
  <pin name="refclk" direction="input" scope="external" />
  <pin name="rst" direction="input" scope="external" />
  <pin name="outclk_0" direction="output" scope="external" />
  <pin name="locked" direction="output" scope="external" />
 </global>
</pinplan>