/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2022  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 0 0 160 144)
	(text "pll_main" (rect 56 -1 87 11)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 128 20 140)(font "Arial" ))
	(port
		(pt 0 72)
		(input)
		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
		(line (pt 0 72)(pt 48 72)(line_width 1))
	)
	(port
		(pt 0 112)
		(input)
		(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
		(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
		(line (pt 0 112)(pt 48 112)(line_width 1))
	)
	(port
		(pt 160 72)
		(output)
		(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
		(line (pt 160 72)(pt 112 72)(line_width 1))
	)
	(port
		(pt 160 112)
		(output)
		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
		(text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
		(line (pt 160 112)(pt 112 112)(line_width 1))
	)
	(drawing
		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
		(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
		(text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
		(text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
		(text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
		(line (pt 48 32)(pt 112 32)(line_width 1))
		(line (pt 112 32)(pt 112 128)(line_width 1))
		(line (pt 48 128)(pt 112 128)(line_width 1))
		(line (pt 48 32)(pt 48 128)(line_width 1))
		(line (pt 49 52)(pt 49 76)(line_width 1))
		(line (pt 50 52)(pt 50 76)(line_width 1))
		(line (pt 49 92)(pt 49 116)(line_width 1))
		(line (pt 50 92)(pt 50 116)(line_width 1))
		(line (pt 111 52)(pt 111 76)(line_width 1))
		(line (pt 110 52)(pt 110 76)(line_width 1))
		(line (pt 111 92)(pt 111 116)(line_width 1))
		(line (pt 110 92)(pt 110 116)(line_width 1))
		(line (pt 0 0)(pt 160 0)(line_width 1))
		(line (pt 160 0)(pt 160 144)(line_width 1))
		(line (pt 0 144)(pt 160 144)(line_width 1))
		(line (pt 0 0)(pt 0 144)(line_width 1))
	)
)
