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Johannes Kutning
2023-10-31 07:47:27 +01:00
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hardware/system/pll/pll_main_sim/aldec/rivierapro_setup.tcl
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# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 21.1 850 linux 2022.08.29.18:38:18
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# pll_main
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "aldec.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If pll_main is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "pll_main"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/datadisk/opt/quartus-lite-21.1.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries
ensure_lib ./libraries/work
vmap work ./libraries/work
ensure_lib ./libraries/altera
vmap altera ./libraries/altera
ensure_lib ./libraries/lpm
vmap lpm ./libraries/lpm
ensure_lib ./libraries/sgate
vmap sgate ./libraries/sgate
ensure_lib ./libraries/altera_mf
vmap altera_mf ./libraries/altera_mf
ensure_lib ./libraries/altera_lnsim
vmap altera_lnsim ./libraries/altera_lnsim
ensure_lib ./libraries/cyclonev
vmap cyclonev ./libraries/cyclonev
ensure_lib ./libraries/cyclonev_hssi
vmap cyclonev_hssi ./libraries/cyclonev_hssi
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h
hardware/system/pll/pll_main_sim/cadence/cds.lib
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DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE altera ./libraries/altera/
DEFINE lpm ./libraries/lpm/
DEFINE sgate ./libraries/sgate/
DEFINE altera_mf ./libraries/altera_mf/
DEFINE altera_lnsim ./libraries/altera_lnsim/
DEFINE cyclonev ./libraries/cyclonev/
DEFINE cyclonev_hssi ./libraries/cyclonev_hssi/
hardware/system/pll/pll_main_sim/cadence/hdl.var
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DEFINE WORK work
hardware/system/pll/pll_main_sim/cadence/ncsim_setup.sh
Executable
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# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 21.1 850 linux 2022.08.29.18:38:18
# ----------------------------------------
# ncsim - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# pll_main
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated files
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
# # into the location from which you launch the simulator, or incorporate
# # into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/cadence/ncsim_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# ncvlog <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/cadence/ncsim_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME=<simulation top> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If pll_main is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 21.1 850 linux 2022.08.29.18:38:18
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="pll_main"
QSYS_SIMDIR="./../"
QUARTUS_INSTALL_DIR="/datadisk/opt/quartus-lite-21.1.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera/
mkdir -p ./libraries/lpm/
mkdir -p ./libraries/sgate/
mkdir -p ./libraries/altera_mf/
mkdir -p ./libraries/altera_lnsim/
mkdir -p ./libraries/cyclonev/
mkdir -p ./libraries/cyclonev_hssi/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
export GENERIC_PARAM_COMPAT_CHECK=1
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
fi
hardware/system/pll/pll_main_sim/mentor/msim_setup.tcl
+278
View File
@@ -0,0 +1,278 @@
# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ----------------------------------------
# Auto-generated simulation script msim_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# pll_main
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "mentor.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If pll_main is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 21.1 850 linux 2022.08.29.18:38:18
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "pll_main"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/datadisk/opt/quartus-lite-21.1.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
ensure_lib ./libraries/altera/
vmap altera ./libraries/altera/
ensure_lib ./libraries/lpm/
vmap lpm ./libraries/lpm/
ensure_lib ./libraries/sgate/
vmap sgate ./libraries/sgate/
ensure_lib ./libraries/altera_mf/
vmap altera_mf ./libraries/altera_mf/
ensure_lib ./libraries/altera_lnsim/
vmap altera_lnsim ./libraries/altera_lnsim/
ensure_lib ./libraries/cyclonev/
vmap cyclonev ./libraries/cyclonev/
ensure_lib ./libraries/cyclonev_hssi/
vmap cyclonev_hssi ./libraries/cyclonev_hssi/
}
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -voptargs=+acc option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -voptargs=+acc
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h
hardware/system/pll/pll_main_sim/pll_main.vho
+307
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@@ -0,0 +1,307 @@
--IP Functional Simulation Model
--VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- You may only use these simulation model output files for simulation
-- purposes and expressly not for synthesis or any other purposes (in which
-- event Intel disclaims all warranties of any kind).
--synopsys translate_off
LIBRARY altera_lnsim;
USE altera_lnsim.altera_lnsim_components.all;
--synthesis_resources = altera_pll 1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pll_main IS
PORT
(
locked : OUT STD_LOGIC;
outclk_0 : OUT STD_LOGIC;
refclk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END pll_main;
ARCHITECTURE RTL OF pll_main IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_pll_main_altera_pll_altera_pll_i_639_locked : STD_LOGIC;
SIGNAL wire_pll_main_altera_pll_altera_pll_i_639_outclk : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_gnd <= '0';
locked <= wire_pll_main_altera_pll_altera_pll_i_639_locked;
outclk_0 <= wire_pll_main_altera_pll_altera_pll_i_639_outclk(0);
pll_main_altera_pll_altera_pll_i_639 : altera_pll
GENERIC MAP (
c_cnt_bypass_en0 => "false",
c_cnt_bypass_en1 => "false",
c_cnt_bypass_en10 => "false",
c_cnt_bypass_en11 => "false",
c_cnt_bypass_en12 => "false",
c_cnt_bypass_en13 => "false",
c_cnt_bypass_en14 => "false",
c_cnt_bypass_en15 => "false",
c_cnt_bypass_en16 => "false",
c_cnt_bypass_en17 => "false",
c_cnt_bypass_en2 => "false",
c_cnt_bypass_en3 => "false",
c_cnt_bypass_en4 => "false",
c_cnt_bypass_en5 => "false",
c_cnt_bypass_en6 => "false",
c_cnt_bypass_en7 => "false",
c_cnt_bypass_en8 => "false",
c_cnt_bypass_en9 => "false",
c_cnt_hi_div0 => 1,
c_cnt_hi_div1 => 1,
c_cnt_hi_div10 => 1,
c_cnt_hi_div11 => 1,
c_cnt_hi_div12 => 1,
c_cnt_hi_div13 => 1,
c_cnt_hi_div14 => 1,
c_cnt_hi_div15 => 1,
c_cnt_hi_div16 => 1,
c_cnt_hi_div17 => 1,
c_cnt_hi_div2 => 1,
c_cnt_hi_div3 => 1,
c_cnt_hi_div4 => 1,
c_cnt_hi_div5 => 1,
c_cnt_hi_div6 => 1,
c_cnt_hi_div7 => 1,
c_cnt_hi_div8 => 1,
c_cnt_hi_div9 => 1,
c_cnt_in_src0 => "ph_mux_clk",
c_cnt_in_src1 => "ph_mux_clk",
c_cnt_in_src10 => "ph_mux_clk",
c_cnt_in_src11 => "ph_mux_clk",
c_cnt_in_src12 => "ph_mux_clk",
c_cnt_in_src13 => "ph_mux_clk",
c_cnt_in_src14 => "ph_mux_clk",
c_cnt_in_src15 => "ph_mux_clk",
c_cnt_in_src16 => "ph_mux_clk",
c_cnt_in_src17 => "ph_mux_clk",
c_cnt_in_src2 => "ph_mux_clk",
c_cnt_in_src3 => "ph_mux_clk",
c_cnt_in_src4 => "ph_mux_clk",
c_cnt_in_src5 => "ph_mux_clk",
c_cnt_in_src6 => "ph_mux_clk",
c_cnt_in_src7 => "ph_mux_clk",
c_cnt_in_src8 => "ph_mux_clk",
c_cnt_in_src9 => "ph_mux_clk",
c_cnt_lo_div0 => 1,
c_cnt_lo_div1 => 1,
c_cnt_lo_div10 => 1,
c_cnt_lo_div11 => 1,
c_cnt_lo_div12 => 1,
c_cnt_lo_div13 => 1,
c_cnt_lo_div14 => 1,
c_cnt_lo_div15 => 1,
c_cnt_lo_div16 => 1,
c_cnt_lo_div17 => 1,
c_cnt_lo_div2 => 1,
c_cnt_lo_div3 => 1,
c_cnt_lo_div4 => 1,
c_cnt_lo_div5 => 1,
c_cnt_lo_div6 => 1,
c_cnt_lo_div7 => 1,
c_cnt_lo_div8 => 1,
c_cnt_lo_div9 => 1,
c_cnt_odd_div_duty_en0 => "false",
c_cnt_odd_div_duty_en1 => "false",
c_cnt_odd_div_duty_en10 => "false",
c_cnt_odd_div_duty_en11 => "false",
c_cnt_odd_div_duty_en12 => "false",
c_cnt_odd_div_duty_en13 => "false",
c_cnt_odd_div_duty_en14 => "false",
c_cnt_odd_div_duty_en15 => "false",
c_cnt_odd_div_duty_en16 => "false",
c_cnt_odd_div_duty_en17 => "false",
c_cnt_odd_div_duty_en2 => "false",
c_cnt_odd_div_duty_en3 => "false",
c_cnt_odd_div_duty_en4 => "false",
c_cnt_odd_div_duty_en5 => "false",
c_cnt_odd_div_duty_en6 => "false",
c_cnt_odd_div_duty_en7 => "false",
c_cnt_odd_div_duty_en8 => "false",
c_cnt_odd_div_duty_en9 => "false",
c_cnt_ph_mux_prst0 => 0,
c_cnt_ph_mux_prst1 => 0,
c_cnt_ph_mux_prst10 => 0,
c_cnt_ph_mux_prst11 => 0,
c_cnt_ph_mux_prst12 => 0,
c_cnt_ph_mux_prst13 => 0,
c_cnt_ph_mux_prst14 => 0,
c_cnt_ph_mux_prst15 => 0,
c_cnt_ph_mux_prst16 => 0,
c_cnt_ph_mux_prst17 => 0,
c_cnt_ph_mux_prst2 => 0,
c_cnt_ph_mux_prst3 => 0,
c_cnt_ph_mux_prst4 => 0,
c_cnt_ph_mux_prst5 => 0,
c_cnt_ph_mux_prst6 => 0,
c_cnt_ph_mux_prst7 => 0,
c_cnt_ph_mux_prst8 => 0,
c_cnt_ph_mux_prst9 => 0,
c_cnt_prst0 => 1,
c_cnt_prst1 => 1,
c_cnt_prst10 => 1,
c_cnt_prst11 => 1,
c_cnt_prst12 => 1,
c_cnt_prst13 => 1,
c_cnt_prst14 => 1,
c_cnt_prst15 => 1,
c_cnt_prst16 => 1,
c_cnt_prst17 => 1,
c_cnt_prst2 => 1,
c_cnt_prst3 => 1,
c_cnt_prst4 => 1,
c_cnt_prst5 => 1,
c_cnt_prst6 => 1,
c_cnt_prst7 => 1,
c_cnt_prst8 => 1,
c_cnt_prst9 => 1,
clock_name_0 => "UNUSED",
clock_name_1 => "UNUSED",
clock_name_2 => "UNUSED",
clock_name_3 => "UNUSED",
clock_name_4 => "UNUSED",
clock_name_5 => "UNUSED",
clock_name_6 => "UNUSED",
clock_name_7 => "UNUSED",
clock_name_8 => "UNUSED",
clock_name_global_0 => "false",
clock_name_global_1 => "false",
clock_name_global_2 => "false",
clock_name_global_3 => "false",
clock_name_global_4 => "false",
clock_name_global_5 => "false",
clock_name_global_6 => "false",
clock_name_global_7 => "false",
clock_name_global_8 => "false",
data_rate => 0,
deserialization_factor => 4,
duty_cycle0 => 50,
duty_cycle1 => 50,
duty_cycle10 => 50,
duty_cycle11 => 50,
duty_cycle12 => 50,
duty_cycle13 => 50,
duty_cycle14 => 50,
duty_cycle15 => 50,
duty_cycle16 => 50,
duty_cycle17 => 50,
duty_cycle2 => 50,
duty_cycle3 => 50,
duty_cycle4 => 50,
duty_cycle5 => 50,
duty_cycle6 => 50,
duty_cycle7 => 50,
duty_cycle8 => 50,
duty_cycle9 => 50,
fractional_vco_multiplier => "false",
m_cnt_bypass_en => "false",
m_cnt_hi_div => 1,
m_cnt_lo_div => 1,
m_cnt_odd_div_duty_en => "false",
mimic_fbclk_type => "gclk",
n_cnt_bypass_en => "false",
n_cnt_hi_div => 1,
n_cnt_lo_div => 1,
n_cnt_odd_div_duty_en => "false",
number_of_clocks => 1,
operation_mode => "direct",
output_clock_frequency0 => "100.000000 MHz",
output_clock_frequency1 => "0 MHz",
output_clock_frequency10 => "0 MHz",
output_clock_frequency11 => "0 MHz",
output_clock_frequency12 => "0 MHz",
output_clock_frequency13 => "0 MHz",
output_clock_frequency14 => "0 MHz",
output_clock_frequency15 => "0 MHz",
output_clock_frequency16 => "0 MHz",
output_clock_frequency17 => "0 MHz",
output_clock_frequency2 => "0 MHz",
output_clock_frequency3 => "0 MHz",
output_clock_frequency4 => "0 MHz",
output_clock_frequency5 => "0 MHz",
output_clock_frequency6 => "0 MHz",
output_clock_frequency7 => "0 MHz",
output_clock_frequency8 => "0 MHz",
output_clock_frequency9 => "0 MHz",
phase_shift0 => "0 ps",
phase_shift1 => "0 ps",
phase_shift10 => "0 ps",
phase_shift11 => "0 ps",
phase_shift12 => "0 ps",
phase_shift13 => "0 ps",
phase_shift14 => "0 ps",
phase_shift15 => "0 ps",
phase_shift16 => "0 ps",
phase_shift17 => "0 ps",
phase_shift2 => "0 ps",
phase_shift3 => "0 ps",
phase_shift4 => "0 ps",
phase_shift5 => "0 ps",
phase_shift6 => "0 ps",
phase_shift7 => "0 ps",
phase_shift8 => "0 ps",
phase_shift9 => "0 ps",
pll_auto_clk_sw_en => "false",
pll_bw_sel => "low",
pll_bwctrl => 0,
pll_clk_loss_sw_en => "false",
pll_clk_sw_dly => 0,
pll_clkin_0_src => "clk_0",
pll_clkin_1_src => "clk_0",
pll_cp_current => 0,
pll_dsm_out_sel => "1st_order",
pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
pll_fbclk_mux_1 => "glb",
pll_fbclk_mux_2 => "fb_1",
pll_fractional_cout => 24,
pll_fractional_division => 1,
pll_m_cnt_in_src => "ph_mux_clk",
pll_manu_clk_sw_en => "false",
pll_output_clk_frequency => "0 MHz",
pll_slf_rst => "false",
pll_subtype => "General",
pll_type => "General",
pll_vco_div => 1,
pll_vcoph_div => 1,
refclk1_frequency => "0 MHz",
reference_clock_frequency => "50.0 MHz",
sim_additional_refclk_cycles_to_lock => 0
)
PORT MAP (
fbclk => wire_gnd,
locked => wire_pll_main_altera_pll_altera_pll_i_639_locked,
outclk => wire_pll_main_altera_pll_altera_pll_i_639_outclk,
refclk => refclk,
rst => rst
);
END RTL; --pll_main
--synopsys translate_on
--VALID FILE
hardware/system/pll/pll_main_sim/synopsys/vcsmx/synopsys_sim.setup
+12
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@@ -0,0 +1,12 @@
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera: ./libraries/altera/
lpm: ./libraries/lpm/
sgate: ./libraries/sgate/
altera_mf: ./libraries/altera_mf/
altera_lnsim: ./libraries/altera_lnsim/
cyclonev: ./libraries/cyclonev/
cyclonev_hssi: ./libraries/cyclonev_hssi/
LIBRARY_SCAN = TRUE
hardware/system/pll/pll_main_sim/synopsys/vcsmx/vcsmx_setup.sh
Executable
+202
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@@ -0,0 +1,202 @@
# (C) 2001-2022 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 21.1 850 linux 2022.08.29.18:38:18
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# pll_main
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated library
# # setup "synopsys_sim.setup" into the location from which you launch the
# # simulator, or incorporate into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# #
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# vlogan <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME="'-top <simulation top>'" \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If pll_main is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 21.1 850 linux 2022.08.29.18:38:18
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="pll_main"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="/datadisk/opt/quartus-lite-21.1.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera/
mkdir -p ./libraries/lpm/
mkdir -p ./libraries/sgate/
mkdir -p ./libraries/altera_mf/
mkdir -p ./libraries/altera_lnsim/
mkdir -p ./libraries/cyclonev/
mkdir -p ./libraries/cyclonev_hssi/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi