initial changes

hardware/signal_processing/add.vhd

@@ -25,12 +25,52 @@ entity add is
     );
 end entity add;
 
+u_add: entity word.add
+    port map (
+        clk => clk,
+        reset => reset,
+        
+        task_start => task_start,
+        task_state => task_state,
+        
+        signal_a_read => signal_a_read,
+        signal_a_readdata => signal_a_readdata,
+        
+        signal_b_read => signal_b_read,
+        signal_b_readdata => signal_b_readdata,
+        
+        signal_write => signal_write,
+        signal_writedata => signal_writedata
+);
+
+        
+    
+    
 architecture rtl of add is
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
+    signal state : integer range 0 to 255;
+    signal reset : integer range 0 to 7;
+    signal start : integer range 0 to 7;
+    signal done : integer range 0 to 7;
+    signal A : STD_LOGIC_VECTOR(31 downto 0);
+    signal B : STD_LOGIC_VECTOR(31 downto 0);
+    signal sum : STD_LOGIC_VECTOR(31 downto 0);
 
 begin
+    
+    u_float_add : entity work.float_add
+        port map (
+            clk => clk,
+            reset => reset,
+            start => start,
+            done => done,
+            A => A,
+            B => B,
+            sum => sum
+        );
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -54,7 +94,15 @@ begin
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
+            signal_a_read <= 'O';
+            signal_b_read <= 'O';
+            signal_write <= 'O';
+            signal_Writedata <= (others => '0');
             index <= 0;
+            state <= 0;
+            sum <= 0;
+            done <= 0;
+            start <= 0;
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
@@ -63,6 +111,8 @@ begin
                 signal_write <= '0';
             when work.task.TASK_RUNNING =>
                 index <= index + 1;
+                --signal_a_read <= '1' ;
+                --signal_b_read <= '1' ;
                 signal_write <= '1';
                 signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>