diff --git a/hardware/signal_processing/add.vhd b/hardware/signal_processing/add.vhd
index 133d56e..06a3c82 100644
--- a/hardware/signal_processing/add.vhd
+++ b/hardware/signal_processing/add.vhd
@@ -50,6 +50,7 @@ architecture rtl of add is
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
+    signal start_proc : integer range 0 to 7;
     signal state : integer range 0 to 255;
     signal reset : integer range 0 to 7;
     signal start : integer range 0 to 7;
@@ -64,10 +65,10 @@ begin
         port map (
             clk => clk,
             reset => reset,
-            start => start,
+            start => start_proc,
             done => done,
-            A => A,
-            B => B,
+            A => signal_a_readdata,
+            B => signal_b_readdata,
             sum => sum
         );
 
@@ -89,6 +90,40 @@ begin
                 end if;
         end case;
     end process task_state_transitions;
+    
+    
+    perform_add : process ( clk, reset ) is
+    begin
+        if (start_proc = '1' or reset = '1' ) then
+            signal_a_read <= '0';
+            signal_b_read <= '0';
+        else if (rising_edge(clk)) then
+            case state is
+                when 0 =>
+                    start <= '1';
+                    signal_a_read <= '1';
+                    A <= signal_a_readdata;
+                    signal_b_read <= '1';
+                    B <= signal_b_readdata;
+                    
+                    if( done = '1' ) then
+                        signal_a_read <= '0';
+                        signal_b_read <= '0';
+                        state <= '2';
+                    end if;
+              when 2 =>
+            
+        end if;
+       
+        
+            
+                    
+                    
+                
+                    
+        end case;
+    end process perform_add;
+    
 
     sync : process ( clk, reset ) is
     begin
@@ -110,9 +145,9 @@ begin
                 index <= 0;
                 signal_write <= '0';
             when work.task.TASK_RUNNING =>
+                start_proc <= '1';
+                
                 index <= index + 1;
-                --signal_a_read <= '1' ;
-                --signal_b_read <= '1' ;
                 signal_write <= '1';
                 signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>