allamaaki80515/signal_processing
1
0
Fork 0
forked from KutningJo/signal_processing_vorlage
Code Pull Requests Activity

Compare commits

base: allamaaki80515:testbranch
Branches Tags
allamaaki80515:master
allamaaki80515:initial
allamaaki80515:testbranch
KutningJo:master
..
compare: allamaaki80515:master
Branches Tags
allamaaki80515:initial
allamaaki80515:testbranch
allamaaki80515:master
KutningJo:master

No commits in common. "testbranch" and "master" have entirely different histories.
testbranch ... master

1 changed files with 5 additions and 40 deletions
Show Stats Expand all files Collapse all files

45
hardware/signal_processing/add.vhd
View File

@ -50,7 +50,6 @@ architecture rtl of add is
signal current_task_state : work.task.State; signal current_task_state : work.task.State;
signal next_task_state : work.task.State; signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN; signal index : integer range 0 to work.task.STREAM_LEN;
signal start_proc : integer range 0 to 7;
signal state : integer range 0 to 255; signal state : integer range 0 to 255;
signal reset : integer range 0 to 7; signal reset : integer range 0 to 7;
signal start : integer range 0 to 7; signal start : integer range 0 to 7;
@ -65,10 +64,10 @@ begin
port map ( port map (
clk => clk, clk => clk,
reset => reset, reset => reset,
start => start_proc, start => start,
done => done, done => done,
A => signal_a_readdata, A => A,
B => signal_b_readdata, B => B,
sum => sum sum => sum
); );
@ -90,40 +89,6 @@ begin
end if; end if;
end case; end case;
end process task_state_transitions; end process task_state_transitions;
perform_add : process ( clk, reset ) is
begin
if (start_proc = '1' or reset = '1' ) then
signal_a_read <= '0';
signal_b_read <= '0';
else if (rising_edge(clk)) then
case state is
when 0 =>
start <= '1';
signal_a_read <= '1';
A <= signal_a_readdata;
signal_b_read <= '1';
B <= signal_b_readdata;
if( done = '1' ) then
signal_a_read <= '0';
signal_b_read <= '0';
state <= '2';
end if;
when 2 =>
end if;
end case;
end process perform_add;
sync : process ( clk, reset ) is sync : process ( clk, reset ) is
begin begin
@ -145,9 +110,9 @@ begin
index <= 0; index <= 0;
signal_write <= '0'; signal_write <= '0';
when work.task.TASK_RUNNING => when work.task.TASK_RUNNING =>
start_proc <= '1';
index <= index + 1; index <= index + 1;
--signal_a_read <= '1' ;
--signal_b_read <= '1' ;
signal_write <= '1'; signal_write <= '1';
signal_writedata <= ( others => '0' ); signal_writedata <= ( others => '0' );
when work.task.TASK_DONE => when work.task.TASK_DONE =>