262 lines
9.6 KiB
VHDL
262 lines
9.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.float.all;
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use work.task.all;
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entity sine is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic; --Startsignal
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task_state : out work.task.State; --Ausgang
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step_size : in work.reg32.word; --Winkelinkrement pro Sample
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phase : in work.reg32.word; --Startwinkel
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amplitude : in work.reg32.word; --Amplitude
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector(31 downto 0)
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);
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end entity sine;
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architecture rtl of sine is
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--Task-FSM
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signal current_task_state : work.task.State := work.task.TASK_IDLE;
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signal next_task_state : work.task.State := work.task.TASK_IDLE;
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signal index : integer range 0 to work.task.STREAM_LEN := 0;
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--Flanken-Erkennung
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signal task_start_d : std_logic := '0';
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signal task_start_re : std_logic := '0';
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--float_sine-IP-core
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signal fs_data_valid : std_logic := '0'; --eingabe
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signal fs_busy : std_logic; -- Steuerung
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signal fs_result_valid : std_logic;
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signal fs_angle : signed(31 downto 0) := (others => '0');
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signal fs_sine : signed(31 downto 0); --Ausgabe
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--Datenpfad
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signal angle_reg : signed(31 downto 0) := (others => '0'); --aktueller Winkel
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signal sine_raw_fp : std_logic_vector(31 downto 0) := (others => '0'); --Ergebnis des IP-Cores
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signal sine_scaled_fp : std_logic_vector(31 downto 0) := (others => '0'); --skaliertes Ergebnis
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--Calc-FSM
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type calc_state_t is (
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C_IDLE,
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C_START,
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C_WAIT,
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C_SCALE,
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C_WRITE
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);
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signal calc_state : calc_state_t := C_IDLE;
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begin
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task_state <= current_task_state;
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--------------------------------------------------------------------------
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-- Task-FSM transitions
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--------------------------------------------------------------------------
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task_state_transitions : process(current_task_state, task_start_re, index, calc_state)
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if task_start_re = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if (index = work.task.STREAM_LEN ) and (calc_state = C_WRITE) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if task_start_re = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process;
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--------------------------------------------------------------------------
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-- float_sine instantiation
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--------------------------------------------------------------------------
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fs_angle <= angle_reg;
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u_float_sine : entity work.float_sine
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generic map (
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ITERATIONS => 8
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)
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port map (
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clk => clk,
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reset => reset,
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data_valid => fs_data_valid, --Eingabe starten
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busy => fs_busy, --Core arbeitet
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result_valid => fs_result_valid, --Ergebnis fertig
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angle => fs_angle, --Eingabewinkel
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sine => fs_sine --Ergebnis
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);
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--------------------------------------------------------------------------
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-- Sync / Datenpfad
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--------------------------------------------------------------------------
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--Multiplikation über: neuer_exponent = sin_exp + (amp_exp -127)
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sync : process(clk, reset)
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variable sin_exp : unsigned(7 downto 0); --Speichern Sinuszahl
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variable amp_exp : unsigned(7 downto 0); --Speichern Amplitude
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variable new_exp : unsigned(7 downto 0); --Speichern neuen Exponenten
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--Exponenten als Integerwerte für Berechnung
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variable sin_e_i : integer range -255 to 511;
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variable amp_e_i : integer range -255 to 511;
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variable new_e_i : integer range -255 to 511;
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begin
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if reset = '1' then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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task_start_d <= '0';
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task_start_re <= '0';
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calc_state <= C_IDLE;
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angle_reg <= (others => '0');
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sine_raw_fp <= (others => '0');
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sine_scaled_fp <= (others => '0');
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fs_data_valid <= '0';
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signal_write <= '0';
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signal_writedata <= (others => '0');
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elsif rising_edge(clk) then
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------------------------------------------------------------------
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-- rising edge detect
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------------------------------------------------------------------
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task_start_re <= task_start and not task_start_d;
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task_start_d <= task_start;
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------------------------------------------------------------------
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-- Defaults
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------------------------------------------------------------------
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signal_write <= '0';
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fs_data_valid <= '0';
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------------------------------------------------------------------
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-- Task-FSM update
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------------------------------------------------------------------
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current_task_state <= next_task_state;
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------------------------------------------------------------------
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-- Berechnungs-FSM
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------------------------------------------------------------------
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case calc_state is
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------------------------------------------------------------------
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-- Start: Sofort mit erstem Winkel beginnen
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------------------------------------------------------------------
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when C_IDLE =>
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if (current_task_state = work.task.TASK_RUNNING) then
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angle_reg <= signed(phase);
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calc_state <= C_START;
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end if;
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------------------------------------------------------------------
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-- Wert in den Core laden, sobald busy='0'
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------------------------------------------------------------------
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when C_START =>
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if fs_busy = '0' then --Wenn Core ist frei
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fs_data_valid <= '1'; --Input-Latch im Core
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calc_state <= C_WAIT;
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end if;
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------------------------------------------------------------------
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-- Warten auf Ergebnis
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------------------------------------------------------------------
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when C_WAIT => --Warten auf Ergebnis
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if fs_result_valid = '1' then
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sine_raw_fp <= std_logic_vector(fs_sine);
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calc_state <= C_SCALE;
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end if;
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------------------------------------------------------------------
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-- Skalierung
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------------------------------------------------------------------
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when C_SCALE =>
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sin_exp := unsigned(sine_raw_fp(30 downto 23)); --Liest die 8 Exponentenbits des Sinuswerts
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amp_exp := unsigned(amplitude(30 downto 23)); --Liese die 8 der Amplitude
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sin_e_i := to_integer(sin_exp); --Umwandlung in Integer
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amp_e_i := to_integer(amp_exp);
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new_e_i := sin_e_i + (amp_e_i - 127); --Eigentliche Multiplikation
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if new_e_i < 0 then -- Falls Wert negativ
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new_exp := (others => '0'); --Setze Wert auf 0
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else
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new_exp := to_unsigned(new_e_i, 8); --Zurückwandeln in 8-Bit-Exponent
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end if;
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--Berechnten Exponenten wieder zusammensetzen
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sine_scaled_fp(31) <= sine_raw_fp(31);
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sine_scaled_fp(30 downto 23) <= std_logic_vector(new_exp);
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sine_scaled_fp(22 downto 0) <= sine_raw_fp(22 downto 0);
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calc_state <= C_WRITE;
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------------------------------------------------------------------
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-- Schreiben + nächsten Winkel
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------------------------------------------------------------------
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when C_WRITE =>
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signal_write <= '1';
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signal_writedata <= sine_scaled_fp;
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if index = work.task.STREAM_LEN then
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calc_state <= C_IDLE;
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else
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angle_reg <= angle_reg + signed(step_size);
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calc_state <= C_START;
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end if;
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end case;
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------------------------------------------------------------------
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-- Index update
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------------------------------------------------------------------
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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when work.task.TASK_RUNNING =>
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if calc_state = C_WRITE then
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if index < work.task.STREAM_LEN then
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index <= index + 1;
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end if;
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end if;
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when work.task.TASK_DONE =>
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index <= 0;
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end case;
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end if;
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end process;
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end architecture rtl;
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