modified makefile to use make commands for testing

makefile

@@ -35,8 +35,11 @@ $(program_obj_filesobj_files): %.o: %.c
 # --------------------------
 # Unit Tests
 # --------------------------
-unitTests:
-	echo "needs to be implemented"
+numbers_tests:
+	$(CC) $(FLAGS) numbers.c bintree.c stack.c unity.c test_numbers.c -o test_numbers
+
+stack_tests:
+	$(CC) $(FLAGS) stack.c unity.c stackunitytest.c -o test_stack
 
 # --------------------------
 # Clean