signal_processing_vorlage/tests/hardware/task_fft/test_task_fft.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.float_pkg.all;

library work;
    use work.reg32.all;
    use work.avalon_slave.all;
    use work.test_utility.all;
    use work.test_avalon_slave.all;
    use work.task.all;
    use work.fft_data.all;
    use work.test_hardware_task.all;

library std;
    use std.env.all;
    use std.textio.all;

entity test_task_fft is
end entity test_task_fft;

architecture test of test_task_fft is

    procedure test_configure( signal clk : in std_logic;
        signal req : out work.avalon_slave.Request;
        signal rsp : in work.avalon_slave.Response ) is

        variable index : integer := 0;
        variable writedata : std_logic_vector( 31 downto 0 );
    begin
        std.textio.write( std.textio.OUTPUT, "    test_configure ... " );
        index := 0;
        writedata := x"08000000"; -- 2^32 / 32
        write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
            index => index, config => writedata );

        index := 1;
        writedata := x"00000000";
        write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
            index => index, config => writedata );

        index := 2;
        writedata := x"40800000"; -- 2 ** 2 = 4 float
        write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
            index => index, config => writedata );

        std.textio.write( std.textio.OUTPUT, TEST_OK );

    end procedure test_configure;

    procedure test_execute( signal clk : in std_logic;
        signal req : out work.avalon_slave.Request;
        signal rsp : in work.avalon_slave.Response;
        signal write : in std_logic;
        signal writedata : in std_logic_vector ) is

        type data_array is array ( natural range <> ) of std_logic_vector( writedata'range );

        variable expected_readdata : std_logic_vector( 31 downto 0 );
        variable index : integer := 0;
        
        variable writedata_fft : integer;
        variable writedata_float : float32;
        variable writedata_real : real;
        variable expected_real : real;
        variable abs_err : real := 0.5e-1;
        variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
        variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
        file data_file : text;
        file data_file_fft : text;
        file data_file_fft_bit_reversed : text;
        variable index_bit_reversed : std_logic_vector( 9 downto 0 );

    begin
        std.textio.write( std.textio.OUTPUT, "    test_execute ... " );

        expected_readdata := to_std_logic_vector( TASK_IDLE, expected_readdata'length );
        assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );

        write_start( clk => clk, req => req );

        expected_readdata := to_std_logic_vector( TASK_RUNNING, expected_readdata'length );
        assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );

        file_open( data_file, "data.py", write_mode );
        std.textio.write( data_file, "float_data = [" );

        file_open( data_file_fft, "fft_out.py", write_mode );
        std.textio.write( data_file_fft, "ftt_out_data = [" );

        while index < STREAM_LEN loop
            wait until falling_edge( clk );
            if ( write = '1' ) then
                result( index ) := writedata;
                writedata_float := to_float( result( index ) );
                writedata_real := to_real( writedata_float );
                std.textio.write( data_file, to_string( writedata_real ) & "," );

                result_fft( index ) := writedata;
                writedata_fft := to_integer(signed(result_fft( index )));
                std.textio.write( data_file_fft, to_string( writedata_fft ) & "," );

                index := index + 1;

            end if;
        end loop;
        std.textio.write( data_file, "]" & LF );
        file_close( data_file );

        std.textio.write( data_file_fft, "]" & LF );
        file_close( data_file_fft );

        while index < STREAM_LEN loop
            writedata_float := to_float( result( index ) );
            writedata_real := to_real( writedata_float );
            expected_real := work.fft_data.expected( index );
            assert_near( writedata_real, expected_real, abs_err );
        end loop;

        file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );
        std.textio.write( data_file_fft_bit_reversed, "ftt_out_data = [" );

        index := 0;
        index_bit_reversed := "0000000000";
        while index < STREAM_LEN loop
                index_bit_reversed :=  std_logic_vector(to_unsigned(index, index_bit_reversed'length));
                index_bit_reversed := index_bit_reversed(0)&index_bit_reversed(1)&index_bit_reversed(2)&index_bit_reversed(3)&index_bit_reversed(4)&index_bit_reversed(5)&index_bit_reversed(6)&index_bit_reversed(7)&index_bit_reversed(8)&index_bit_reversed(9);
                index := to_integer(unsigned(index_bit_reversed));

                writedata_fft := to_integer(signed(result_fft( index )));

                std.textio.write( data_file_fft_bit_reversed, to_string( writedata_fft ) & "," );

                index_bit_reversed := index_bit_reversed(0)&index_bit_reversed(1)&index_bit_reversed(2)&index_bit_reversed(3)&index_bit_reversed(4)&index_bit_reversed(5)&index_bit_reversed(6)&index_bit_reversed(7)&index_bit_reversed(8)&index_bit_reversed(9);              
                index := to_integer(unsigned(index_bit_reversed));

                index := index + 1;

        end loop;
        std.textio.write( data_file_fft_bit_reversed, "]" & LF );
        file_close( data_file_fft_bit_reversed );

        std.textio.write( std.textio.OUTPUT, TEST_OK );
    end procedure test_execute;

    signal clk : std_logic := '0';
    signal reset : std_logic := '1';

    signal req : work.avalon_slave.Request;
    signal rsp : work.avalon_slave.Response;
    
    signal signal_read : std_logic;
    signal signal_readdata : std_logic_vector( 31 downto 0 );
    signal index_output : integer range 0 to 1023;
   
    type input_data_array is array ( natural range <> ) of std_logic_vector(31 downto 0);

constant input_data: input_data_array (0 to 1023) := (x"40daf8d9",x"400464d6",x"40707518",x"412f4d86",x"bf2c6338",x"3fe858d0",x"40a93c0d",x"411d1b42",x"40ae6f95",x"40f76d48",x"414b45bb",x"bf80c95c",x"40653088",x"40cf8814",x"404a5d41",x"40c8b99e",x"c0a2d52e",x"c097b780",x"c0618ef7",x"c0e982c7",x"c024cbd1",x"bf618a97",x"bfe51ce1",x"3fb47578",x"c11df822",x"c08594f9",x"403fd955",x"c0aa7966",x"bff13a72",x"40132fc6",x"bf2de1e2",x"4061d87f",x"c06ac864",x"bf711298",x"4011b5da",x"4110d242",x"402cc82f",x"413cdf10",x"4025bc6a",x"41356772",x"404ff73c",x"40ab30ae",x"412170aa",x"40326cc2",x"412caa7b",x"c09488ea",x"c092507c",x"c06f49b3",x"bf0d20d4",x"402ca19a",x"bff135fa",x"3fafefe8",x"c1197ab4",x"c10ca7e7",x"c0e7237f",x"c091c47c",x"c066436a",x"3d914c40",x"c0999d9d",x"bf82f570",x"c0e55fe3",x"c05520da",x"40605138",x"c021210c",x"40c78efa",x"bfd5f3be",x"3fd3d6b1",x"3fe55ef8",x"408eaf1a",x"bf99eb4a",x"400acf31",x"40ca0d76",x"c06f7ec0",x"c0156063",x"3fcbe0a0",x"4009d2a1",x"3feb3b7c",x"40f5953d",x"bfbe458a",x"4046b62c",x"c113cc05",x"c087d026",x"bfccd099",x"3f8155a6",x"c0f1209c",x"c11042a8",x"c0bf6ebc",x"3fc1136c",x"c1464c70",x"c12df84f",x"c10aa752",x"c0b06ec4",x"c08650e5",x"bfd06e2c",x"c0d2c72e",x"c0e3e57a",x"c08b3546",x"bfb0d585",x"403febfc",x"be122ec9",x"3fe57176",x"3fe53e46",x"4108cf43",x"3f01a6a4",x"403c3ee3",x"4017e4ad",x"40eb2c13",x"3ef0621c",x"40eba5ee",x"c09499f7",x"c054478c",x"bfac1b65",x"40b68a12",x"c11be620",x"c09ceffc",x"3f01c820",x"c0e2f412",x"c0a78f83",x"c0a41d0e",x"c05f2f6a",x"c0f98a04",x"c0fba274",x"c0fe9e26",x"c0a150f5",x"c07b476d",x"3e009bf0",x"c055c84d",x"bf142c8e",x"be67ec78",x"3dd2c0cc",x"3f011ca1",x"4077ccb8",x"3fc47cab",x"4107f727",x"bfd2f436",x"3f229404",x"403e75a3",x"405653d7",x"4055b80b",x"406c1a7a",x"408bf1a0",x"bf2951d8",x"3f5e1db9",x"3f0ceda0",x"bd48f1c8",x"40078de7",x"c0d40bfe",x"c047cafb",x"c02e4bc7",x"c03dd5ae",x"c0142d40",x"beadb830",x"c088264a",x"3eddd418",x"c07f2957",x"c0377cbb",x"3e6054b0",x"c0a43500",x"bfaf530d",x"404a35ab",x"c09d1b4d",x"3f137065",x"4029875f",x"40824c49",x"408786ed",x"40d59fa1",x"408f5241",x"410b56f8",x"40942720",x"4132ff7d",x"3f1748c0",x"407ed381",x"40886ce3",x"406f5b24",x"404b8482",x"4095a7c8",x"bfc0d0ee",x"c04d5c67",x"bef1981b",x"3f9b8e53",x"3f010d6c",x"40816b01",x"c03be548",x"bfe2e631",x"bf50b956",x"3fcb2630",x"c10cc7d7",x"c0ea1e79",x"c0996e64",x"bf4c0708",x"40df4d51",x"c082593a",x"3f911f18",x"40f2c5fe",x"3f240db0",x"407dd077",x"413a600e",x"beb58cb0",x"40014757",x"40b022de",x"4135f6b6",x"40a286ee",x"40c11cb7",x"410ced4a",x"bf935600",x"404d3b0a",x"41359a58",x"c09f481d",x"3da888b0",x"40ff55c1",x"bf8628b1",x"40559908",x"bfb1b61e",x"407bbeaa",x"c0a9e96e",x"c0fac5df",x"c0be2c58",x"c10fbd7b",x"c059776c",x"3ff23d0b",x"c0eef375",x"bfe29bf2",x"4021884b",x"3f07d900",x"40b22610",x"3daed460",x"4030b71f",x"40bf6a6e",x"3f9d6390",x"408a28d2",x"40a9da87",x"41306adc",x"40827670",x"40adf30d",x"40d3bb17",x"40c4c47c",x"40b053dc",x"411a898e",x"c041170a",x"3f230783",x"40b82185",x"c056f0a5",x"c0b27b9c",x"c08a913e",x"c0b1592a",x"c0ebbd8e",x"c08110fa",x"bf837a24",x"c082cffd",x"3fe6a02c",x"c0938da1",x"c03e4892",x"4015ee20",x"c04f04bf",x"bfba869f",x"be97d71c",x"408be6b0",x"beaf6864",x"4090daba",x"c089e406",x"3f9bc832",x"4128abc9",x"3f81999a",x"412b3f77",x"3fae413e",x"4092db9f",x"40ea6812",x"3fd46a6c",x"409e2e5c",x"c0696f7e",x"c018fc04",x"c07bf051",x"c0e7a797",x"c0c227ae",x"c05904cc",x"bfda9871",x"40492d22",x"c0d14fa4",x"c073a299",x"bfe46994",x"c0c18767",x"3e32b7c0",x"c1122d14",x"c140dffe",x"c12987f0",x"c1008994",x"c07640e8",x"bf0eaa08",x"c07e82be",x"bf9edaa2",x"40063aa3",x"c028afad",x"c03ef2d1",x"3f67c42c",x"405ec244",x"405c9d20",x"4040f756",x"401b9b21",x"406c6bbe",x"40543aca",x"410be00e",x"c0f35646",x"c101ed3c",x"c04273b8",x"40945b7d",x"c0ffe39e",x"c0d78e2c",x"c1123262",x"c0f7522a",x"c112c3f2",x"c154d998",x"c1537448",x"c14ae788",x"c0e56daa",x"bfee3c9e",x"c0b09aa8",x"c052c2eb",x"bf4acce8",x"c0fa6c22",x"c0a14e7e",x"c09a94ba",x"bf8d327f",x"4035c5b3",x"c03ea671",x"3f71fbc5",x"40f09f04",x"3fb6559a",x"40402833",x"40f2c9b0",x"3ffdacc4",x"40302c24",x"41118f2c",x"c0811c5a",x"3e833d44",x"40f77617",x"c0ceb437",x"c0011eb4",x"bf68a1b3",x"3f87bf94",x"c1035b72",x"c088c46d",x"3fad9ee0",x"c0eddc85",x"c11520cf",x"c0a3ae5c",x"c07f6a7e",x"406f84db",x"c0ab7840",x"40733e14",x"c06a6562",x"3ffd4321",x"bf8c24dd",x"3f927763",x"4042c5e0",x"bebc7778",x"3e71d150",x"3f1aedcc",x"4063fe9d",x"410fa150",x"3fd93bda",x"408ca422",x"409fc375",x"40b22aa6",x"40983215",x"4077de82",x"40ef5ece",x"3ff40f95",x"3ffbcd45",x"408f19d2",x"c0a83ae8",x"bfa0b156",x"bf18a1bb",x"40504818",x"c02d22cb",x"c0066d63",x"c006b74c",x"4018adb5",x"c049e8d2",x"3fd9b518",x"c112ab95",x"c03af28c",x"3f5a6b62",x"4075f720",x"c0b999c4",x"3ec39b04",x"405bb566",x"41145003",x"3e03bb30",x"c041d4aa",x"40565bb8",x"41476c6c",x"3de36dc0",x"40a020bd",x"414ce41b",x"40863b44",x"41129a5f",x"c028844a",x"c02b6540",x"c010647f",x"3feab4d4",x"41121b63",x"c0a16e58",x"bf2a96f9",x"4012eae9",x"c07973bb",x"c0b21017",x"c012342e",x"3ee9c9d8",x"c09d65e0",x"c0b6db34",x"c00e2a4a",x"bca9a3c0",x"402e6279",x"bf4f67fd",x"3fd545b1",x"3ff1c82a",x"4008f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    signal signal_write : std_logic;
    signal signal_writedata : std_logic_vector( 31 downto 0 );

begin

    dut : entity work.task_fft
        port map (
            clk => clk,
            reset => reset,

            address => req.address,
            read => req.read,
            readdata => rsp.readdata,
            write => req.write,
            writedata => req.writedata,

            signal_read => signal_read,
            signal_readdata => signal_readdata,
            
            signal_write => signal_write,
            signal_writedata => signal_writedata
        );

    clk <= not clk after 10 ns;

    p_number_input_sample: process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            index_output <= 1; 
            signal_readdata <= input_data(0);
        elsif ( rising_edge( clk ) ) then
            if signal_read = '1' then
               if index_output /= 1023 then
	     	  index_output <= index_output + 1;       
               end if;      
              signal_readdata <= input_data(index_output);
            end if;
        end if;
    end process p_number_input_sample;

    reset_release : process is
    begin
         wait for 435 ns;
         reset <= '0';
         wait;
    end process reset_release;

    stimulus: process is
        variable address : std_logic_vector( 3 downto 0 );
        variable level : std_logic_vector( 31 downto 0 );
        variable readdata : std_logic_vector( 31 downto 0 );
        variable writedata : std_logic_vector( 31 downto 0 );
        variable expected_readdata : std_logic_vector( 31 downto 0 );
    begin
        std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );
        std.textio.write( std.textio.OUTPUT, "Starting test_task_fft" & LF );
        wait until falling_edge( reset );
        wait until falling_edge( clk );

        test_configure( clk => clk, req => req, rsp => rsp );
        test_execute( clk => clk, req => req, rsp => rsp,

        write => signal_write, writedata => signal_writedata );

        wait until falling_edge( signal_write );

        wait for 200 ns;
        std.textio.write( std.textio.OUTPUT, "Finished test_task_fft" & LF );
        std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );

	std.env.finish( 0 );
    end process stimulus;
end architecture test;