signal_processing_vorlage/tests/hardware/task_rand/Makefile

vhdl_srcs = ../../../hardware/system/reg32.vhd \
			../../../hardware/system/avalon_slave.vhd \
			../../../hardware/system/avalon_slave_transitions.vhd \
			../../../hardware/system/task.vhd \
			../../../hardware/system/hardware_task_control.vhd \
			../../../hardware/system/data_channel_control.vhd \
			../../../hardware/system/data_sink_mux.vhd \
			../../../hardware/system/data_source_mux.vhd \
            ../../../hardware/system/fifo.vhd \
            ../../../hardware/system/data_channel.vhd \
            ../../../hardware/signal_processing/rand.vhd \
            ../../../hardware/system/task_rand.vhd \
			../test_utility.vhd \
			../test_avalon_slave.vhd \
			../test_hardware_task.vhd \
			../test_data_channel.vhd \
			../../data/rand.vhd \
            test_task_rand.vhd \

main = test_task_rand
expected_data = ../../data/rand.py

include ../data_tests.mk