signal_processing/tests/hardware/task_sine/Makefile

vhdl_srcs = ../../../hardware/system/reg32.vhd \
            ../../../hardware/system/task.vhd \
            ../../../hardware/system/avalon_slave.vhd \
            ../../../hardware/system/avalon_slave_transitions.vhd \
            ../../../hardware/system/float.vhd \
            ../../../hardware/system/hardware_task_control.vhd \
            ../../../hardware/system/data_channel_control.vhd \
            ../../../hardware/system/data_sink_mux.vhd \
            ../../../hardware/system/data_source_mux.vhd \
            ../../../hardware/system/fifo.vhd \
            ../../../hardware/system/data_channel.vhd \
            ../../../hardware/system/cordic_pkg.vhd \
            ../../../hardware/system/cordic.vhd \
            ../../../hardware/system/fixed_sine.vhd \
            ../../../hardware/system/float_sine.vhd \
            ../../../hardware/signal_processing/sine.vhd \
            ../../../hardware/system/task_sine.vhd \
            ../test_utility.vhd \
            ../test_avalon_slave.vhd \
            ../test_hardware_task.vhd \
            ../test_data_channel.vhd \
            ../../data/sine.vhd \
            test_task_sine.vhd \

main = test_task_sine
expected_data = ../../data/sine.py

include ../data_tests.mk