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-
-
-
- module SdfUnit2 #(
- parameter WIDTH = 16,
- parameter BF_RH = 0
- )(
- input clock,
- input reset,
- input di_en,
- input [WIDTH-1:0] di_re,
- input [WIDTH-1:0] di_im,
- output reg do_en,
- output reg [WIDTH-1:0] do_re,
- output reg [WIDTH-1:0] do_im
- );
-
-
-
-
- reg bf_en;
- wire[WIDTH-1:0] x0_re;
- wire[WIDTH-1:0] x0_im;
- wire[WIDTH-1:0] x1_re;
- wire[WIDTH-1:0] x1_im;
- wire[WIDTH-1:0] y0_re;
- wire[WIDTH-1:0] y0_im;
- wire[WIDTH-1:0] y1_re;
- wire[WIDTH-1:0] y1_im;
- wire[WIDTH-1:0] db_di_re;
- wire[WIDTH-1:0] db_di_im;
- wire[WIDTH-1:0] db_do_re;
- wire[WIDTH-1:0] db_do_im;
- wire[WIDTH-1:0] bf_sp_re;
- wire[WIDTH-1:0] bf_sp_im;
- reg bf_sp_en;
-
-
-
-
- always @(posedge clock or posedge reset) begin
- if (reset) begin
- bf_en <= 1'b0;
- end else begin
- bf_en <= di_en ? ~bf_en : 1'b0;
- end
- end
-
-
- assign x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
- assign x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
- assign x1_re = bf_en ? di_re : {WIDTH{1'bx}};
- assign x1_im = bf_en ? di_im : {WIDTH{1'bx}};
-
- Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
- .x0_re (x0_re ),
- .x0_im (x0_im ),
- .x1_re (x1_re ),
- .x1_im (x1_im ),
- .y0_re (y0_re ),
- .y0_im (y0_im ),
- .y1_re (y1_re ),
- .y1_im (y1_im )
- );
-
- DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
- .clock (clock ),
- .di_re (db_di_re ),
- .di_im (db_di_im ),
- .do_re (db_do_re ),
- .do_im (db_do_im )
- );
-
- assign db_di_re = bf_en ? y1_re : di_re;
- assign db_di_im = bf_en ? y1_im : di_im;
- assign bf_sp_re = bf_en ? y0_re : db_do_re;
- assign bf_sp_im = bf_en ? y0_im : db_do_im;
-
- always @(posedge clock or posedge reset) begin
- if (reset) begin
- bf_sp_en <= 1'b0;
- do_en <= 1'b0;
- end else begin
- bf_sp_en <= di_en;
- do_en <= bf_sp_en;
- end
- end
-
- always @(posedge clock) begin
- do_re <= bf_sp_re;
- do_im <= bf_sp_im;
- end
-
- endmodule
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