From 85a540315025cc0bb8e7f9ea1b7261b662d21c03 Mon Sep 17 00:00:00 2001 From: binnerda82916 Date: Tue, 17 Dec 2024 22:33:34 +0100 Subject: [PATCH] funktional mit abweichung --- hardware/signal_processing/fft.vhd | 81 ++++++++++++++++-------------- 1 file changed, 44 insertions(+), 37 deletions(-) diff --git a/hardware/signal_processing/fft.vhd b/hardware/signal_processing/fft.vhd index 2207f1f..320e421 100644 --- a/hardware/signal_processing/fft.vhd +++ b/hardware/signal_processing/fft.vhd @@ -52,6 +52,7 @@ type fft_state_dec is ( FFT_STATE_IDLE, + FFT_STATE_READ, FFT_STATE_FILL_IP_CORE, FFT_STATE_GET_IP_CORE, FFT_STATE_SORT, @@ -98,18 +99,17 @@ signal value_data_out_mag : std_logic_vector(31 downto 0); signal value_data_out_mag_float : std_logic_vector(31 downto 0); signal value_data_out_mag_float_scaled : std_logic_vector(31 downto 0); + type memory_array is array (0 to work.task.STREAM_LEN - 1) of std_logic_vector(31 downto 0); signal memory : memory_array := (others => (others => '0')); signal sorted_memory : memory_array := (others => (others => '0')); signal bitsort_index : integer range 0 to work.task.STREAM_LEN; - signal bitsort_index_temp: integer range 0 to work.task.STREAM_LEN; - signal bitsort_index_out : integer range 0 to work.task.STREAM_LEN; - signal input_vector : std_logic_vector(work.task.STREAM_LEN-1 downto 0); - signal reversed_bits : std_logic_vector(work.task.STREAM_LEN-1 downto 0); + signal a_vec : std_logic_vector(9 downto 0); -- Vector for 1024 range signal b_vec : std_logic_vector(9 downto 0); -- Reversed vector - signal a : integer range 0 to 1023 := 100; -- Example input integer + signal b : integer range 0 to 1023; -- Reversed integer output + signal read_wait : integer range 0 to 4; signal value_mag_in_ready: std_logic; signal value_mag_out_ready: std_logic; @@ -195,8 +195,9 @@ end process sync; fft : process (clk, reset) is - variable fifo_in : signed(31 downto 0); - variable fifo_out : signed(31 downto 0); + + + begin -- Bei Reset alle Signale zurücksetzen if ( reset = '1' ) then @@ -210,8 +211,8 @@ flag_index <= '0'; a_vec <= (others => '0'); b_vec <= (others => '0'); - b <= 0; - a <= 0; + b <= 0; + read_wait <= 0; -- Für jeden Takt fft_state Zustandsmaschine aufrufen. elsif ( rising_edge( clk ) ) then @@ -220,49 +221,55 @@ flag_index <= '0'; if ( current_task_state = work.task.TASK_RUNNING ) then fft_state <= FFT_STATE_FILL_IP_CORE; + signal_read <= '1'; end if; + when FFT_STATE_READ => + + read_wait <= read_wait + 1; + if (read_wait = 1) then + fft_state <= FFT_STATE_FILL_IP_CORE; + + end if; + + when FFT_STATE_FILL_IP_CORE => value_data_in_ready <= '1'; - signal_read <= '1'; value_data_in_real <= signal_readdata; - if value_data_in_real(30 downto 23) = "00000000" then - value_data_in_real_scaled_fixed <= to_fixed(value_data_in_real); + value_data_in_real_scaled(31) <= value_data_in_real(31); + value_data_in_real_scaled(22 downto 0) <= std_logic_vector(signed(value_data_in_real(22 downto 0))); + if value_data_in_real_scaled(30 downto 23) = "00000000" then + value_data_in_real_scaled(30 downto 23) <= std_logic_vector(signed(value_data_in_real(30 downto 23))); else - fifo_in(31) := value_data_in_real(31); - fifo_in(30 downto 23) := signed(value_data_in_real(30 downto 23)) - 4; - fifo_in(22 downto 0) := signed(value_data_in_real(22 downto 0)); - value_data_in_real_scaled_fixed <= to_fixed(std_logic_vector(fifo_in)); - + value_data_in_real_scaled(30 downto 23) <= std_logic_vector(signed(value_data_in_real(30 downto 23)) - 4); end if; + value_data_in_real_scaled_fixed <= to_fixed(std_logic_vector(value_data_in_real_scaled)); if (value_data_out_ready = '1') then fft_state <= FFT_STATE_GET_IP_CORE; + signal_read <= '0'; + value_mag_in_ready <= '1'; end if; when FFT_STATE_GET_IP_CORE => - signal_read <= '0'; - - value_mag_in_ready <= '1'; - - value_data_out_mag_float <= to_float(value_data_out_mag); - - value_data_out_mag_float_scaled(31) <= value_data_out_mag_float(31); - value_data_out_mag_float_scaled(22 downto 0) <= std_logic_vector(signed(value_data_out_mag_float(22 downto 0))); - if value_data_out_mag_float(30 downto 23) = "00000000" then - value_data_out_mag_float_scaled(30 downto 23) <= std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 4); - else - value_data_out_mag_float_scaled(30 downto 23) <= std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 5); - end if; - - - memory(index) <= value_data_out_mag_float_scaled; - if (value_mag_out_ready = '1') then + + value_data_out_mag_float <= to_float(value_data_out_mag); + + value_data_out_mag_float_scaled(31) <= value_data_out_mag_float(31); + value_data_out_mag_float_scaled(22 downto 0) <= std_logic_vector(signed(value_data_out_mag_float(22 downto 0))); + if value_data_out_mag_float(30 downto 23) = "00000000" then + value_data_out_mag_float_scaled(30 downto 23) <= std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 4); + else + value_data_out_mag_float_scaled(30 downto 23) <= std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 5); + end if; + + memory(index) <= value_data_out_mag_float_scaled; + flag_index <= '1'; end if; @@ -270,8 +277,7 @@ --value_data_in_ready <= '0'; flag_index <= '0'; bitsort_index <= 0; - bitsort_index_temp <= 0; - bitsort_index_out <= 0; + fft_state <= FFT_STATE_SORT; end if; @@ -285,7 +291,8 @@ b <= to_integer(unsigned(b_vec)); - sorted_memory(b) <= memory(bitsort_index); + sorted_memory(bitsort_index) <= memory(b); + bitsort_index <= bitsort_index + 1; if (bitsort_index = work.task.STREAM_LEN - 1) then