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binnerda82916 2024-12-18 10:34:40 +01:00
parent 85a5403150
commit fe4bf812ef
1 changed files with 63 additions and 24 deletions
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87
hardware/signal_processing/fft.vhd
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@ -46,6 +46,26 @@
architecture rtl of fft is
function mag_scale(pre_scale : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable value_data_out_mag_float : std_logic_vector(31 downto 0);
variable value_data_out_mag_float_scaled : std_logic_vector(31 downto 0);
begin
value_data_out_mag_float := to_float(pre_scale);
value_data_out_mag_float_scaled(31) := value_data_out_mag_float(31);
value_data_out_mag_float_scaled(22 downto 0) := std_logic_vector(signed(value_data_out_mag_float(22 downto 0)));
if value_data_out_mag_float(30 downto 23) = "00000000" then
value_data_out_mag_float_scaled(30 downto 23) := std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 4);
else
value_data_out_mag_float_scaled(30 downto 23) := std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 5);
end if;
return value_data_out_mag_float_scaled;
end function;
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
@ -90,8 +110,9 @@
-- Eigene Steuersignale.
signal value_data_in_ready : std_logic;
signal value_data_in_real : std_logic_vector(31 downto 0);
signal value_data_in_real_scaled : std_logic_vector(31 downto 0);
--signal value_data_in_real_scaled : std_logic_vector(31 downto 0);
signal value_data_in_real_scaled_fixed : std_logic_vector(31 downto 0);
--signal value_data_in_real_temp : std_logic_vector(31 downto 0);
signal value_data_in_imag : std_logic_vector(31 downto 0);
signal value_data_out_ready : std_logic;
signal value_data_out_real : std_logic_vector(31 downto 0);
@ -100,16 +121,16 @@
signal value_data_out_mag_float : std_logic_vector(31 downto 0);
signal value_data_out_mag_float_scaled : std_logic_vector(31 downto 0);
type memory_array is array (0 to work.task.STREAM_LEN - 1) of std_logic_vector(31 downto 0);
type memory_array is array (0 to work.task.STREAM_LEN) of std_logic_vector(31 downto 0);
signal memory : memory_array := (others => (others => '0'));
signal sorted_memory : memory_array := (others => (others => '0'));
signal bitsort_index : integer range 0 to work.task.STREAM_LEN;
signal a_vec : std_logic_vector(9 downto 0); -- Vector for 1024 range
signal b_vec : std_logic_vector(9 downto 0); -- Reversed vector
--signal a_vec : std_logic_vector(9 downto 0); -- Vector for 1024 range
--signal b_vec : std_logic_vector(9 downto 0); -- Reversed vector
signal b : integer range 0 to 1023; -- Reversed integer output
signal read_wait : integer range 0 to 4;
--signal b : integer range 0 to 1023; -- Reversed integer output
signal read_wait : integer range 0 to (2048);
signal value_mag_in_ready: std_logic;
signal value_mag_out_ready: std_logic;
@ -196,6 +217,12 @@
fft : process (clk, reset) is
variable value_data_in_real_scaled : std_logic_vector(31 downto 0);
variable value_data_in_real_temp : std_logic_vector(31 downto 0);
variable a_vec : std_logic_vector(9 downto 0); -- Reversed vector
variable b_vec : std_logic_vector(9 downto 0); -- Reversed vector
variable b : integer range 0 to 1023;
variable mag_temp : std_logic_vector(31 downto 0);
begin
@ -209,9 +236,8 @@
signal_write <= '0';
signal_read <= '0';
flag_index <= '0';
a_vec <= (others => '0');
b_vec <= (others => '0');
b <= 0;
read_wait <= 0;
-- Für jeden Takt fft_state Zustandsmaschine aufrufen.
@ -235,18 +261,25 @@
when FFT_STATE_FILL_IP_CORE =>
value_data_in_ready <= '1';
--value_data_in_real <= signal_readdata;
read_wait <= read_wait + 1;
value_data_in_real_scaled(31) := signal_readdata(31);
value_data_in_real_scaled(22 downto 0) := std_logic_vector(signed(signal_readdata(22 downto 0)));
if value_data_in_real_scaled(30 downto 23) = "00000000" then
value_data_in_real_scaled(30 downto 23) := std_logic_vector(signed(signal_readdata(30 downto 23)));
else
value_data_in_real_scaled(30 downto 23) := std_logic_vector(signed(signal_readdata(30 downto 23)) - 4);
end if;
value_data_in_real_temp := to_fixed(std_logic_vector(value_data_in_real_scaled));
value_data_in_real_scaled_fixed <= value_data_in_real_temp;
value_data_in_ready <= '1';
value_data_in_real <= signal_readdata;
value_data_in_real_scaled(31) <= value_data_in_real(31);
value_data_in_real_scaled(22 downto 0) <= std_logic_vector(signed(value_data_in_real(22 downto 0)));
if value_data_in_real_scaled(30 downto 23) = "00000000" then
value_data_in_real_scaled(30 downto 23) <= std_logic_vector(signed(value_data_in_real(30 downto 23)));
else
value_data_in_real_scaled(30 downto 23) <= std_logic_vector(signed(value_data_in_real(30 downto 23)) - 4);
end if;
value_data_in_real_scaled_fixed <= to_fixed(std_logic_vector(value_data_in_real_scaled));
if (value_data_out_ready = '1') then
fft_state <= FFT_STATE_GET_IP_CORE;
@ -266,9 +299,14 @@
value_data_out_mag_float_scaled(30 downto 23) <= std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 4);
else
value_data_out_mag_float_scaled(30 downto 23) <= std_logic_vector(signed(value_data_out_mag_float(30 downto 23)) + 5);
if (read_wait > 2) then
memory(index) <= value_data_out_mag_float_scaled;
end if;
memory(index) <= value_data_out_mag_float_scaled;
end if;
flag_index <= '1';
end if;
@ -283,13 +321,13 @@
when FFT_STATE_SORT =>
a_vec <= std_logic_vector(to_unsigned(bitsort_index, a_vec'length));
a_vec := std_logic_vector(to_unsigned(bitsort_index, a_vec'length));
for i in 0 to 9 loop
b_vec(i) <= a_vec(9 - i);
b_vec(i) := a_vec(9 - i);
end loop;
b <= to_integer(unsigned(b_vec));
b := to_integer(unsigned(b_vec));
sorted_memory(bitsort_index) <= memory(b);
@ -298,10 +336,11 @@
if (bitsort_index = work.task.STREAM_LEN - 1) then
bitsort_index <= 0;
fft_state <= FFT_STATE_WRITE;
end if;
when FFT_STATE_WRITE =>
signal_write <= '1';
signal_writedata <= sorted_memory(bitsort_index);
bitsort_index <= bitsort_index + 1;