Lösung des ESY6/A Praktikums "signal_processing".
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pll_main.bsf 3.4KB

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  1. /*
  2. WARNING: Do NOT edit the input and output ports in this file in a text
  3. editor if you plan to continue editing the block that represents it in
  4. the Block Editor! File corruption is VERY likely to occur.
  5. */
  6. /*
  7. Copyright (C) 2022 Intel Corporation. All rights reserved.
  8. Your use of Intel Corporation's design tools, logic functions
  9. and other software and tools, and any partner logic
  10. functions, and any output files from any of the foregoing
  11. (including device programming or simulation files), and any
  12. associated documentation or information are expressly subject
  13. to the terms and conditions of the Intel Program License
  14. Subscription Agreement, the Intel Quartus Prime License Agreement,
  15. the Intel FPGA IP License Agreement, or other applicable license
  16. agreement, including, without limitation, that your use is for
  17. the sole purpose of programming logic devices manufactured by
  18. Intel and sold by Intel or its authorized distributors. Please
  19. refer to the applicable agreement for further details, at
  20. https://fpgasoftware.intel.com/eula.
  21. */
  22. (header "symbol" (version "1.1"))
  23. (symbol
  24. (rect 0 0 160 144)
  25. (text "pll_main" (rect 56 -1 87 11)(font "Arial" (font_size 10)))
  26. (text "inst" (rect 8 128 20 140)(font "Arial" ))
  27. (port
  28. (pt 0 72)
  29. (input)
  30. (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
  31. (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
  32. (line (pt 0 72)(pt 48 72)(line_width 1))
  33. )
  34. (port
  35. (pt 0 112)
  36. (input)
  37. (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
  38. (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
  39. (line (pt 0 112)(pt 48 112)(line_width 1))
  40. )
  41. (port
  42. (pt 160 72)
  43. (output)
  44. (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
  45. (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
  46. (line (pt 160 72)(pt 112 72)(line_width 1))
  47. )
  48. (port
  49. (pt 160 112)
  50. (output)
  51. (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
  52. (text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
  53. (line (pt 160 112)(pt 112 112)(line_width 1))
  54. )
  55. (drawing
  56. (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
  57. (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
  58. (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
  59. (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
  60. (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
  61. (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
  62. (text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
  63. (text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
  64. (text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
  65. (line (pt 48 32)(pt 112 32)(line_width 1))
  66. (line (pt 112 32)(pt 112 128)(line_width 1))
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  81. )
  82. )