signal_processing_vorlage/hardware/system/float_sine.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;

library work;
    use work.cordic_pkg.all;
    use work.float.all;

entity float_sine is
    generic (
        ITERATIONS : positive    -- Number of CORDIC iterations
    );
    port (
        clk : in std_logic;
        reset : in std_logic;

        data_valid : in std_logic;  --# load new input data
        busy : out std_logic; --# generating new result
        result_valid : out std_logic; --# flag when result is valid
        angle : in signed(31 downto 0); -- angle in brads (2**size brads = 2*pi radians)
        sine : out signed(31 downto 0)
    );
end entity float_sine;

architecture rtl of float_sine is
    signal fixed : signed( 31 downto 0 );
begin

    u_fixed_sine : entity work.fixed_sine
        generic map (
          SIZE => 32,
          ITERATIONS => 8,
          FRAC_BITS => 31
        )
        port map (
            clock => clk,
            reset => reset,

            data_valid => data_valid,
            busy => busy,
            result_valid => result_valid,
            angle => angle,
            sine => fixed
          );

    sine <= signed( to_float( std_logic_vector( fixed ) ) );

end architecture;