Initial commit
This commit is contained in:
Johannes Kutning
@@ -0,0 +1,82 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2022 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 0 0 160 144)
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(text "pll_main" (rect 56 -1 87 11)(font "Arial" (font_size 10)))
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(text "inst" (rect 8 128 20 140)(font "Arial" ))
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(port
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(pt 0 72)
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(input)
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(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
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(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
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(line (pt 0 72)(pt 48 72)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
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(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
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(line (pt 0 112)(pt 48 112)(line_width 1))
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)
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(port
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(pt 160 72)
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(output)
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(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
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(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
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(line (pt 160 72)(pt 112 72)(line_width 1))
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)
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(port
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(pt 160 112)
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(output)
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(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
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(text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
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(line (pt 160 112)(pt 112 112)(line_width 1))
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)
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(drawing
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(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
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(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
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(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
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(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
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(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
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(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
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(text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
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(text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
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(text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
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(line (pt 48 32)(pt 112 32)(line_width 1))
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(line (pt 112 32)(pt 112 128)(line_width 1))
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(line (pt 48 128)(pt 112 128)(line_width 1))
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(line (pt 48 32)(pt 48 128)(line_width 1))
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(line (pt 49 52)(pt 49 76)(line_width 1))
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(line (pt 50 52)(pt 50 76)(line_width 1))
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(line (pt 49 92)(pt 49 116)(line_width 1))
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(line (pt 50 92)(pt 50 116)(line_width 1))
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(line (pt 111 52)(pt 111 76)(line_width 1))
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(line (pt 110 52)(pt 110 76)(line_width 1))
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(line (pt 111 92)(pt 111 116)(line_width 1))
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(line (pt 110 92)(pt 110 116)(line_width 1))
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(line (pt 0 0)(pt 160 0)(line_width 1))
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(line (pt 160 0)(pt 160 144)(line_width 1))
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(line (pt 0 144)(pt 160 144)(line_width 1))
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(line (pt 0 0)(pt 0 144)(line_width 1))
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)
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)
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@@ -0,0 +1,9 @@
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component pll_main is
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port (
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refclk : in std_logic := 'X'; -- clk
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rst : in std_logic := 'X'; -- reset
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outclk_0 : out std_logic; -- clk
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locked : out std_logic -- export
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);
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end component pll_main;
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@@ -0,0 +1,13 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<pinplan
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variation_name="pll_main"
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megafunction_name="ALTERA_PLL"
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intended_family="Cyclone V"
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specifies="all_ports">
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<global>
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<pin name="refclk" direction="input" scope="external" />
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<pin name="rst" direction="input" scope="external" />
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<pin name="outclk_0" direction="output" scope="external" />
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<pin name="locked" direction="output" scope="external" />
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</global>
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</pinplan>
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@@ -0,0 +1,337 @@
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_NAME "altera_pll"
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_VERSION "21.1"
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_ENV "mwpim"
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set_global_assignment -library "pll_main" -name MISC_FILE [file join $::quartus(qip_path) "pll_main.cmp"]
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_QSYS_MODE "UNKNOWN"
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_NAME "cGxsX21haW4="
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_VERSION "MjEuMQ=="
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set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_NAME "cGxsX21haW5fMDAwMg=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_VERSION "MjEuMQ=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
|
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
|
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set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Ng==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MywzLDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDMwLDIwMDAsMzAwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2NsayxmYWxzZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
|
||||
|
||||
set_global_assignment -library "pll_main" -name VHDL_FILE [file join $::quartus(qip_path) "pll_main.vhd"]
|
||||
set_global_assignment -library "pll_main" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_main/pll_main_0002.v"]
|
||||
set_global_assignment -library "pll_main" -name QIP_FILE [file join $::quartus(qip_path) "pll_main/pll_main_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_ENV "mwpim"
|
||||
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_VERSION "21.1"
|
||||
set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "lib_pll_main" -name SPD_FILE [file join $::quartus(sip_path) "pll_main.spd"]
|
||||
|
||||
set_global_assignment -library "lib_pll_main" -name MISC_FILE [file join $::quartus(sip_path) "pll_main_sim/pll_main.vho"]
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<simPackage>
|
||||
<file path="pll_main_sim/pll_main.vho" type="VHDL" />
|
||||
<topLevel name="pll_main" />
|
||||
<deviceFamily name="cyclonev" />
|
||||
</simPackage>
|
||||
@@ -0,0 +1,271 @@
|
||||
-- megafunction wizard: %PLL Intel FPGA IP v21.1%
|
||||
-- GENERATION: XML
|
||||
-- pll_main.vhd
|
||||
|
||||
-- Generated using ACDS version 21.1 850
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity pll_main is
|
||||
port (
|
||||
refclk : in std_logic := '0'; -- refclk.clk
|
||||
rst : in std_logic := '0'; -- reset.reset
|
||||
outclk_0 : out std_logic; -- outclk0.clk
|
||||
locked : out std_logic -- locked.export
|
||||
);
|
||||
end entity pll_main;
|
||||
|
||||
architecture rtl of pll_main is
|
||||
component pll_main_0002 is
|
||||
port (
|
||||
refclk : in std_logic := 'X'; -- clk
|
||||
rst : in std_logic := 'X'; -- reset
|
||||
outclk_0 : out std_logic; -- clk
|
||||
locked : out std_logic -- export
|
||||
);
|
||||
end component pll_main_0002;
|
||||
|
||||
begin
|
||||
|
||||
pll_main_inst : component pll_main_0002
|
||||
port map (
|
||||
refclk => refclk, -- refclk.clk
|
||||
rst => rst, -- reset.reset
|
||||
outclk_0 => outclk_0, -- outclk0.clk
|
||||
locked => locked -- locked.export
|
||||
);
|
||||
|
||||
end architecture rtl; -- of pll_main
|
||||
-- Retrieval info: <?xml version="1.0"?>
|
||||
--<!--
|
||||
-- Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
-- ************************************************************
|
||||
-- Copyright (C) 1991-2022 Altera Corporation
|
||||
-- Any megafunction design, and related net list (encrypted or decrypted),
|
||||
-- support information, device programming or simulation file, and any other
|
||||
-- associated documentation or information provided by Altera or a partner
|
||||
-- under Altera's Megafunction Partnership Program may be used only to
|
||||
-- program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
-- use of such megafunction design, net list, support information, device
|
||||
-- programming or simulation file, or any other related documentation or
|
||||
-- information is prohibited for any other purpose, including, but not
|
||||
-- limited to modification, reverse engineering, de-compiling, or use with
|
||||
-- any other silicon devices, unless such use is explicitly licensed under
|
||||
-- a separate agreement with Altera or a megafunction partner. Title to
|
||||
-- the intellectual property, including patents, copyrights, trademarks,
|
||||
-- trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
-- net list, support information, device programming or simulation file, or
|
||||
-- any other related documentation or information provided by Altera or a
|
||||
-- megafunction partner, remains with Altera, the megafunction partner, or
|
||||
-- their respective licensors. No other licenses, including any licenses
|
||||
-- needed under any third party's intellectual property, are provided herein.
|
||||
---->
|
||||
-- Retrieval info: <instance entity-name="altera_pll" version="21.1" >
|
||||
-- Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
-- Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
|
||||
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
|
||||
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
|
||||
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
|
||||
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
|
||||
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
-- Retrieval info: <generic name="gui_use_locked" value="true" />
|
||||
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
|
||||
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
|
||||
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
|
||||
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
|
||||
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
|
||||
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
|
||||
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
|
||||
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
|
||||
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
|
||||
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
|
||||
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
|
||||
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
|
||||
-- Retrieval info: <generic name="gui_phout_division" value="1" />
|
||||
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
|
||||
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
|
||||
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
|
||||
-- Retrieval info: <generic name="gui_dps_num" value="1" />
|
||||
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
|
||||
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
|
||||
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
|
||||
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
|
||||
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
|
||||
-- Retrieval info: <generic name="gui_active_clk" value="false" />
|
||||
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
|
||||
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
|
||||
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
|
||||
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
|
||||
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
|
||||
-- Retrieval info: </instance>
|
||||
-- IPFS_FILES : pll_main.vho
|
||||
-- RELATED_FILES: pll_main.vhd, pll_main_0002.v
|
||||
@@ -0,0 +1,4 @@
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_main_0002*|altera_pll:altera_pll_i*|*"
|
||||
|
||||
set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_main_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_main_0002*|altera_pll:altera_pll_i*|*"
|
||||
@@ -0,0 +1,87 @@
|
||||
`timescale 1ns/10ps
|
||||
module pll_main_0002(
|
||||
|
||||
// interface 'refclk'
|
||||
input wire refclk,
|
||||
|
||||
// interface 'reset'
|
||||
input wire rst,
|
||||
|
||||
// interface 'outclk0'
|
||||
output wire outclk_0,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked
|
||||
);
|
||||
|
||||
altera_pll #(
|
||||
.fractional_vco_multiplier("false"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(1),
|
||||
.output_clock_frequency0("100.000000 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("0 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("0 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
.duty_cycle2(50),
|
||||
.output_clock_frequency3("0 MHz"),
|
||||
.phase_shift3("0 ps"),
|
||||
.duty_cycle3(50),
|
||||
.output_clock_frequency4("0 MHz"),
|
||||
.phase_shift4("0 ps"),
|
||||
.duty_cycle4(50),
|
||||
.output_clock_frequency5("0 MHz"),
|
||||
.phase_shift5("0 ps"),
|
||||
.duty_cycle5(50),
|
||||
.output_clock_frequency6("0 MHz"),
|
||||
.phase_shift6("0 ps"),
|
||||
.duty_cycle6(50),
|
||||
.output_clock_frequency7("0 MHz"),
|
||||
.phase_shift7("0 ps"),
|
||||
.duty_cycle7(50),
|
||||
.output_clock_frequency8("0 MHz"),
|
||||
.phase_shift8("0 ps"),
|
||||
.duty_cycle8(50),
|
||||
.output_clock_frequency9("0 MHz"),
|
||||
.phase_shift9("0 ps"),
|
||||
.duty_cycle9(50),
|
||||
.output_clock_frequency10("0 MHz"),
|
||||
.phase_shift10("0 ps"),
|
||||
.duty_cycle10(50),
|
||||
.output_clock_frequency11("0 MHz"),
|
||||
.phase_shift11("0 ps"),
|
||||
.duty_cycle11(50),
|
||||
.output_clock_frequency12("0 MHz"),
|
||||
.phase_shift12("0 ps"),
|
||||
.duty_cycle12(50),
|
||||
.output_clock_frequency13("0 MHz"),
|
||||
.phase_shift13("0 ps"),
|
||||
.duty_cycle13(50),
|
||||
.output_clock_frequency14("0 MHz"),
|
||||
.phase_shift14("0 ps"),
|
||||
.duty_cycle14(50),
|
||||
.output_clock_frequency15("0 MHz"),
|
||||
.phase_shift15("0 ps"),
|
||||
.duty_cycle15(50),
|
||||
.output_clock_frequency16("0 MHz"),
|
||||
.phase_shift16("0 ps"),
|
||||
.duty_cycle16(50),
|
||||
.output_clock_frequency17("0 MHz"),
|
||||
.phase_shift17("0 ps"),
|
||||
.duty_cycle17(50),
|
||||
.pll_type("General"),
|
||||
.pll_subtype("General")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_0}),
|
||||
.locked (locked),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
.refclk (refclk)
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1 @@
|
||||
pll_main_sim/pll_main.vho
|
||||
@@ -0,0 +1,284 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 21.1 850 linux 2022.08.29.18:38:18
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script rivierapro_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll_main
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Altera simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "aldec.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog -sv2k5 <your compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll_main is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "pll_main"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/datadisk/opt/quartus-lite-21.1.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
||||
} else {
|
||||
}
|
||||
|
||||
set Aldec "Riviera"
|
||||
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
|
||||
set Aldec "Active"
|
||||
}
|
||||
|
||||
if { [ string match "Active" $Aldec ] } {
|
||||
scripterconf -tcl
|
||||
createdesign "$TOP_LEVEL_NAME" "."
|
||||
opendesign "$TOP_LEVEL_NAME"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries
|
||||
ensure_lib ./libraries/work
|
||||
vmap work ./libraries/work
|
||||
ensure_lib ./libraries/altera
|
||||
vmap altera ./libraries/altera
|
||||
ensure_lib ./libraries/lpm
|
||||
vmap lpm ./libraries/lpm
|
||||
ensure_lib ./libraries/sgate
|
||||
vmap sgate ./libraries/sgate
|
||||
ensure_lib ./libraries/altera_mf
|
||||
vmap altera_mf ./libraries/altera_mf
|
||||
ensure_lib ./libraries/altera_lnsim
|
||||
vmap altera_lnsim ./libraries/altera_lnsim
|
||||
ensure_lib ./libraries/cyclonev
|
||||
vmap cyclonev ./libraries/cyclonev
|
||||
ensure_lib ./libraries/cyclonev_hssi
|
||||
vmap cyclonev_hssi ./libraries/cyclonev_hssi
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
echo "\[exec\] dev_com"
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
|
||||
vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
|
||||
vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
|
||||
vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
echo "\[exec\] com"
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
echo "\[exec\] elab"
|
||||
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -dbg -O2 option
|
||||
alias elab_debug {
|
||||
echo "\[exec\] elab_debug"
|
||||
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -dbg -O2
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
@@ -0,0 +1,18 @@
|
||||
|
||||
DEFINE std $CDS_ROOT/tools/inca/files/STD/
|
||||
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
|
||||
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
|
||||
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
|
||||
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
|
||||
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
|
||||
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
|
||||
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
|
||||
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
|
||||
DEFINE work ./libraries/work/
|
||||
DEFINE altera ./libraries/altera/
|
||||
DEFINE lpm ./libraries/lpm/
|
||||
DEFINE sgate ./libraries/sgate/
|
||||
DEFINE altera_mf ./libraries/altera_mf/
|
||||
DEFINE altera_lnsim ./libraries/altera_lnsim/
|
||||
DEFINE cyclonev ./libraries/cyclonev/
|
||||
DEFINE cyclonev_hssi ./libraries/cyclonev_hssi/
|
||||
@@ -0,0 +1,2 @@
|
||||
|
||||
DEFINE WORK work
|
||||
+202
@@ -0,0 +1,202 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 21.1 850 linux 2022.08.29.18:38:18
|
||||
|
||||
# ----------------------------------------
|
||||
# ncsim - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll_main
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated files
|
||||
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
|
||||
# # into the location from which you launch the simulator, or incorporate
|
||||
# # into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/cadence/ncsim_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# ncvlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/cadence/ncsim_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME=<simulation top> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll_main is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 21.1 850 linux 2022.08.29.18:38:18
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="pll_main"
|
||||
QSYS_SIMDIR="./../"
|
||||
QUARTUS_INSTALL_DIR="/datadisk/opt/quartus-lite-21.1.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
mkdir -p ./libraries/work/
|
||||
mkdir -p ./libraries/altera/
|
||||
mkdir -p ./libraries/lpm/
|
||||
mkdir -p ./libraries/sgate/
|
||||
mkdir -p ./libraries/altera_mf/
|
||||
mkdir -p ./libraries/altera_lnsim/
|
||||
mkdir -p ./libraries/cyclonev/
|
||||
mkdir -p ./libraries/cyclonev_hssi/
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
|
||||
ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
|
||||
ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
export GENERIC_PARAM_COMPAT_CHECK=1
|
||||
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
@@ -0,0 +1,278 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ----------------------------------------
|
||||
# Auto-generated simulation script msim_setup.tcl
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll_main
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level script that compiles Altera simulation libraries and
|
||||
# the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "mentor.do", and modify the text as directed.
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator.
|
||||
# #
|
||||
# set QSYS_SIMDIR <script generation output directory>
|
||||
# #
|
||||
# # Source the generated IP simulation script.
|
||||
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
|
||||
# #
|
||||
# # Set any compilation options you require (this is unusual).
|
||||
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
|
||||
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
|
||||
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
|
||||
# #
|
||||
# # Call command to compile the Quartus EDA simulation library.
|
||||
# dev_com
|
||||
# #
|
||||
# # Call command to compile the Quartus-generated IP simulation files.
|
||||
# com
|
||||
# #
|
||||
# # Add commands to compile all design files and testbench files, including
|
||||
# # the top level. (These are all the files required for simulation other
|
||||
# # than the files compiled by the Quartus-generated IP simulation script)
|
||||
# #
|
||||
# vlog <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # Set the top-level simulation or testbench module/entity name, which is
|
||||
# # used by the elab command to elaborate the top level.
|
||||
# #
|
||||
# set TOP_LEVEL_NAME <simulation top>
|
||||
# #
|
||||
# # Set any elaboration options you require.
|
||||
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
|
||||
# #
|
||||
# # Call command to elaborate your design and testbench.
|
||||
# elab
|
||||
# #
|
||||
# # Run the simulation.
|
||||
# run -a
|
||||
# #
|
||||
# # Report success to the shell.
|
||||
# exit -code 0
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll_main is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 21.1 850 linux 2022.08.29.18:38:18
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize variables
|
||||
if ![info exists SYSTEM_INSTANCE_NAME] {
|
||||
set SYSTEM_INSTANCE_NAME ""
|
||||
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
|
||||
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
|
||||
}
|
||||
|
||||
if ![info exists TOP_LEVEL_NAME] {
|
||||
set TOP_LEVEL_NAME "pll_main"
|
||||
}
|
||||
|
||||
if ![info exists QSYS_SIMDIR] {
|
||||
set QSYS_SIMDIR "./../"
|
||||
}
|
||||
|
||||
if ![info exists QUARTUS_INSTALL_DIR] {
|
||||
set QUARTUS_INSTALL_DIR "/datadisk/opt/quartus-lite-21.1.1/quartus/"
|
||||
}
|
||||
|
||||
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
|
||||
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
|
||||
}
|
||||
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
|
||||
set USER_DEFINED_ELAB_OPTIONS ""
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Initialize simulation properties - DO NOT MODIFY!
|
||||
set ELAB_OPTIONS ""
|
||||
set SIM_OPTIONS ""
|
||||
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
|
||||
} else {
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Copy ROM/RAM files to simulation directory
|
||||
alias file_copy {
|
||||
echo "\[exec\] file_copy"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Create compilation libraries
|
||||
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
|
||||
ensure_lib ./libraries/
|
||||
ensure_lib ./libraries/work/
|
||||
vmap work ./libraries/work/
|
||||
vmap work_lib ./libraries/work/
|
||||
if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
|
||||
ensure_lib ./libraries/altera/
|
||||
vmap altera ./libraries/altera/
|
||||
ensure_lib ./libraries/lpm/
|
||||
vmap lpm ./libraries/lpm/
|
||||
ensure_lib ./libraries/sgate/
|
||||
vmap sgate ./libraries/sgate/
|
||||
ensure_lib ./libraries/altera_mf/
|
||||
vmap altera_mf ./libraries/altera_mf/
|
||||
ensure_lib ./libraries/altera_lnsim/
|
||||
vmap altera_lnsim ./libraries/altera_lnsim/
|
||||
ensure_lib ./libraries/cyclonev/
|
||||
vmap cyclonev ./libraries/cyclonev/
|
||||
ensure_lib ./libraries/cyclonev_hssi/
|
||||
vmap cyclonev_hssi ./libraries/cyclonev_hssi/
|
||||
}
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile device library files
|
||||
alias dev_com {
|
||||
echo "\[exec\] dev_com"
|
||||
if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
|
||||
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv" -work altera_lnsim
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
|
||||
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
|
||||
}
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile the design files in correct order
|
||||
alias com {
|
||||
echo "\[exec\] com"
|
||||
eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate top level design
|
||||
alias elab {
|
||||
echo "\[exec\] elab"
|
||||
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Elaborate the top level design with -voptargs=+acc option
|
||||
alias elab_debug {
|
||||
echo "\[exec\] elab_debug"
|
||||
eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
|
||||
}
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design
|
||||
alias ld "
|
||||
dev_com
|
||||
com
|
||||
elab
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Compile all the design files and elaborate the top level design with -voptargs=+acc
|
||||
alias ld_debug "
|
||||
dev_com
|
||||
com
|
||||
elab_debug
|
||||
"
|
||||
|
||||
# ----------------------------------------
|
||||
# Print out user commmand line aliases
|
||||
alias h {
|
||||
echo "List Of Command Line Aliases"
|
||||
echo
|
||||
echo "file_copy -- Copy ROM/RAM files to simulation directory"
|
||||
echo
|
||||
echo "dev_com -- Compile device library files"
|
||||
echo
|
||||
echo "com -- Compile the design files in correct order"
|
||||
echo
|
||||
echo "elab -- Elaborate top level design"
|
||||
echo
|
||||
echo "elab_debug -- Elaborate the top level design with -voptargs=+acc option"
|
||||
echo
|
||||
echo "ld -- Compile all the design files and elaborate the top level design"
|
||||
echo
|
||||
echo "ld_debug -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
|
||||
echo
|
||||
echo
|
||||
echo
|
||||
echo "List Of Variables"
|
||||
echo
|
||||
echo "TOP_LEVEL_NAME -- Top level module name."
|
||||
echo " For most designs, this should be overridden"
|
||||
echo " to enable the elab/elab_debug aliases."
|
||||
echo
|
||||
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
|
||||
echo
|
||||
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
|
||||
echo
|
||||
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
|
||||
echo
|
||||
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
|
||||
echo
|
||||
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
|
||||
}
|
||||
file_copy
|
||||
h
|
||||
@@ -0,0 +1,307 @@
|
||||
--IP Functional Simulation Model
|
||||
--VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
-- You may only use these simulation model output files for simulation
|
||||
-- purposes and expressly not for synthesis or any other purposes (in which
|
||||
-- event Intel disclaims all warranties of any kind).
|
||||
|
||||
|
||||
--synopsys translate_off
|
||||
|
||||
LIBRARY altera_lnsim;
|
||||
USE altera_lnsim.altera_lnsim_components.all;
|
||||
|
||||
--synthesis_resources = altera_pll 1
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
ENTITY pll_main IS
|
||||
PORT
|
||||
(
|
||||
locked : OUT STD_LOGIC;
|
||||
outclk_0 : OUT STD_LOGIC;
|
||||
refclk : IN STD_LOGIC;
|
||||
rst : IN STD_LOGIC
|
||||
);
|
||||
END pll_main;
|
||||
|
||||
ARCHITECTURE RTL OF pll_main IS
|
||||
|
||||
ATTRIBUTE synthesis_clearbox : natural;
|
||||
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
|
||||
SIGNAL wire_gnd : STD_LOGIC;
|
||||
SIGNAL wire_pll_main_altera_pll_altera_pll_i_639_locked : STD_LOGIC;
|
||||
SIGNAL wire_pll_main_altera_pll_altera_pll_i_639_outclk : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
BEGIN
|
||||
|
||||
wire_gnd <= '0';
|
||||
locked <= wire_pll_main_altera_pll_altera_pll_i_639_locked;
|
||||
outclk_0 <= wire_pll_main_altera_pll_altera_pll_i_639_outclk(0);
|
||||
pll_main_altera_pll_altera_pll_i_639 : altera_pll
|
||||
GENERIC MAP (
|
||||
c_cnt_bypass_en0 => "false",
|
||||
c_cnt_bypass_en1 => "false",
|
||||
c_cnt_bypass_en10 => "false",
|
||||
c_cnt_bypass_en11 => "false",
|
||||
c_cnt_bypass_en12 => "false",
|
||||
c_cnt_bypass_en13 => "false",
|
||||
c_cnt_bypass_en14 => "false",
|
||||
c_cnt_bypass_en15 => "false",
|
||||
c_cnt_bypass_en16 => "false",
|
||||
c_cnt_bypass_en17 => "false",
|
||||
c_cnt_bypass_en2 => "false",
|
||||
c_cnt_bypass_en3 => "false",
|
||||
c_cnt_bypass_en4 => "false",
|
||||
c_cnt_bypass_en5 => "false",
|
||||
c_cnt_bypass_en6 => "false",
|
||||
c_cnt_bypass_en7 => "false",
|
||||
c_cnt_bypass_en8 => "false",
|
||||
c_cnt_bypass_en9 => "false",
|
||||
c_cnt_hi_div0 => 1,
|
||||
c_cnt_hi_div1 => 1,
|
||||
c_cnt_hi_div10 => 1,
|
||||
c_cnt_hi_div11 => 1,
|
||||
c_cnt_hi_div12 => 1,
|
||||
c_cnt_hi_div13 => 1,
|
||||
c_cnt_hi_div14 => 1,
|
||||
c_cnt_hi_div15 => 1,
|
||||
c_cnt_hi_div16 => 1,
|
||||
c_cnt_hi_div17 => 1,
|
||||
c_cnt_hi_div2 => 1,
|
||||
c_cnt_hi_div3 => 1,
|
||||
c_cnt_hi_div4 => 1,
|
||||
c_cnt_hi_div5 => 1,
|
||||
c_cnt_hi_div6 => 1,
|
||||
c_cnt_hi_div7 => 1,
|
||||
c_cnt_hi_div8 => 1,
|
||||
c_cnt_hi_div9 => 1,
|
||||
c_cnt_in_src0 => "ph_mux_clk",
|
||||
c_cnt_in_src1 => "ph_mux_clk",
|
||||
c_cnt_in_src10 => "ph_mux_clk",
|
||||
c_cnt_in_src11 => "ph_mux_clk",
|
||||
c_cnt_in_src12 => "ph_mux_clk",
|
||||
c_cnt_in_src13 => "ph_mux_clk",
|
||||
c_cnt_in_src14 => "ph_mux_clk",
|
||||
c_cnt_in_src15 => "ph_mux_clk",
|
||||
c_cnt_in_src16 => "ph_mux_clk",
|
||||
c_cnt_in_src17 => "ph_mux_clk",
|
||||
c_cnt_in_src2 => "ph_mux_clk",
|
||||
c_cnt_in_src3 => "ph_mux_clk",
|
||||
c_cnt_in_src4 => "ph_mux_clk",
|
||||
c_cnt_in_src5 => "ph_mux_clk",
|
||||
c_cnt_in_src6 => "ph_mux_clk",
|
||||
c_cnt_in_src7 => "ph_mux_clk",
|
||||
c_cnt_in_src8 => "ph_mux_clk",
|
||||
c_cnt_in_src9 => "ph_mux_clk",
|
||||
c_cnt_lo_div0 => 1,
|
||||
c_cnt_lo_div1 => 1,
|
||||
c_cnt_lo_div10 => 1,
|
||||
c_cnt_lo_div11 => 1,
|
||||
c_cnt_lo_div12 => 1,
|
||||
c_cnt_lo_div13 => 1,
|
||||
c_cnt_lo_div14 => 1,
|
||||
c_cnt_lo_div15 => 1,
|
||||
c_cnt_lo_div16 => 1,
|
||||
c_cnt_lo_div17 => 1,
|
||||
c_cnt_lo_div2 => 1,
|
||||
c_cnt_lo_div3 => 1,
|
||||
c_cnt_lo_div4 => 1,
|
||||
c_cnt_lo_div5 => 1,
|
||||
c_cnt_lo_div6 => 1,
|
||||
c_cnt_lo_div7 => 1,
|
||||
c_cnt_lo_div8 => 1,
|
||||
c_cnt_lo_div9 => 1,
|
||||
c_cnt_odd_div_duty_en0 => "false",
|
||||
c_cnt_odd_div_duty_en1 => "false",
|
||||
c_cnt_odd_div_duty_en10 => "false",
|
||||
c_cnt_odd_div_duty_en11 => "false",
|
||||
c_cnt_odd_div_duty_en12 => "false",
|
||||
c_cnt_odd_div_duty_en13 => "false",
|
||||
c_cnt_odd_div_duty_en14 => "false",
|
||||
c_cnt_odd_div_duty_en15 => "false",
|
||||
c_cnt_odd_div_duty_en16 => "false",
|
||||
c_cnt_odd_div_duty_en17 => "false",
|
||||
c_cnt_odd_div_duty_en2 => "false",
|
||||
c_cnt_odd_div_duty_en3 => "false",
|
||||
c_cnt_odd_div_duty_en4 => "false",
|
||||
c_cnt_odd_div_duty_en5 => "false",
|
||||
c_cnt_odd_div_duty_en6 => "false",
|
||||
c_cnt_odd_div_duty_en7 => "false",
|
||||
c_cnt_odd_div_duty_en8 => "false",
|
||||
c_cnt_odd_div_duty_en9 => "false",
|
||||
c_cnt_ph_mux_prst0 => 0,
|
||||
c_cnt_ph_mux_prst1 => 0,
|
||||
c_cnt_ph_mux_prst10 => 0,
|
||||
c_cnt_ph_mux_prst11 => 0,
|
||||
c_cnt_ph_mux_prst12 => 0,
|
||||
c_cnt_ph_mux_prst13 => 0,
|
||||
c_cnt_ph_mux_prst14 => 0,
|
||||
c_cnt_ph_mux_prst15 => 0,
|
||||
c_cnt_ph_mux_prst16 => 0,
|
||||
c_cnt_ph_mux_prst17 => 0,
|
||||
c_cnt_ph_mux_prst2 => 0,
|
||||
c_cnt_ph_mux_prst3 => 0,
|
||||
c_cnt_ph_mux_prst4 => 0,
|
||||
c_cnt_ph_mux_prst5 => 0,
|
||||
c_cnt_ph_mux_prst6 => 0,
|
||||
c_cnt_ph_mux_prst7 => 0,
|
||||
c_cnt_ph_mux_prst8 => 0,
|
||||
c_cnt_ph_mux_prst9 => 0,
|
||||
c_cnt_prst0 => 1,
|
||||
c_cnt_prst1 => 1,
|
||||
c_cnt_prst10 => 1,
|
||||
c_cnt_prst11 => 1,
|
||||
c_cnt_prst12 => 1,
|
||||
c_cnt_prst13 => 1,
|
||||
c_cnt_prst14 => 1,
|
||||
c_cnt_prst15 => 1,
|
||||
c_cnt_prst16 => 1,
|
||||
c_cnt_prst17 => 1,
|
||||
c_cnt_prst2 => 1,
|
||||
c_cnt_prst3 => 1,
|
||||
c_cnt_prst4 => 1,
|
||||
c_cnt_prst5 => 1,
|
||||
c_cnt_prst6 => 1,
|
||||
c_cnt_prst7 => 1,
|
||||
c_cnt_prst8 => 1,
|
||||
c_cnt_prst9 => 1,
|
||||
clock_name_0 => "UNUSED",
|
||||
clock_name_1 => "UNUSED",
|
||||
clock_name_2 => "UNUSED",
|
||||
clock_name_3 => "UNUSED",
|
||||
clock_name_4 => "UNUSED",
|
||||
clock_name_5 => "UNUSED",
|
||||
clock_name_6 => "UNUSED",
|
||||
clock_name_7 => "UNUSED",
|
||||
clock_name_8 => "UNUSED",
|
||||
clock_name_global_0 => "false",
|
||||
clock_name_global_1 => "false",
|
||||
clock_name_global_2 => "false",
|
||||
clock_name_global_3 => "false",
|
||||
clock_name_global_4 => "false",
|
||||
clock_name_global_5 => "false",
|
||||
clock_name_global_6 => "false",
|
||||
clock_name_global_7 => "false",
|
||||
clock_name_global_8 => "false",
|
||||
data_rate => 0,
|
||||
deserialization_factor => 4,
|
||||
duty_cycle0 => 50,
|
||||
duty_cycle1 => 50,
|
||||
duty_cycle10 => 50,
|
||||
duty_cycle11 => 50,
|
||||
duty_cycle12 => 50,
|
||||
duty_cycle13 => 50,
|
||||
duty_cycle14 => 50,
|
||||
duty_cycle15 => 50,
|
||||
duty_cycle16 => 50,
|
||||
duty_cycle17 => 50,
|
||||
duty_cycle2 => 50,
|
||||
duty_cycle3 => 50,
|
||||
duty_cycle4 => 50,
|
||||
duty_cycle5 => 50,
|
||||
duty_cycle6 => 50,
|
||||
duty_cycle7 => 50,
|
||||
duty_cycle8 => 50,
|
||||
duty_cycle9 => 50,
|
||||
fractional_vco_multiplier => "false",
|
||||
m_cnt_bypass_en => "false",
|
||||
m_cnt_hi_div => 1,
|
||||
m_cnt_lo_div => 1,
|
||||
m_cnt_odd_div_duty_en => "false",
|
||||
mimic_fbclk_type => "gclk",
|
||||
n_cnt_bypass_en => "false",
|
||||
n_cnt_hi_div => 1,
|
||||
n_cnt_lo_div => 1,
|
||||
n_cnt_odd_div_duty_en => "false",
|
||||
number_of_clocks => 1,
|
||||
operation_mode => "direct",
|
||||
output_clock_frequency0 => "100.000000 MHz",
|
||||
output_clock_frequency1 => "0 MHz",
|
||||
output_clock_frequency10 => "0 MHz",
|
||||
output_clock_frequency11 => "0 MHz",
|
||||
output_clock_frequency12 => "0 MHz",
|
||||
output_clock_frequency13 => "0 MHz",
|
||||
output_clock_frequency14 => "0 MHz",
|
||||
output_clock_frequency15 => "0 MHz",
|
||||
output_clock_frequency16 => "0 MHz",
|
||||
output_clock_frequency17 => "0 MHz",
|
||||
output_clock_frequency2 => "0 MHz",
|
||||
output_clock_frequency3 => "0 MHz",
|
||||
output_clock_frequency4 => "0 MHz",
|
||||
output_clock_frequency5 => "0 MHz",
|
||||
output_clock_frequency6 => "0 MHz",
|
||||
output_clock_frequency7 => "0 MHz",
|
||||
output_clock_frequency8 => "0 MHz",
|
||||
output_clock_frequency9 => "0 MHz",
|
||||
phase_shift0 => "0 ps",
|
||||
phase_shift1 => "0 ps",
|
||||
phase_shift10 => "0 ps",
|
||||
phase_shift11 => "0 ps",
|
||||
phase_shift12 => "0 ps",
|
||||
phase_shift13 => "0 ps",
|
||||
phase_shift14 => "0 ps",
|
||||
phase_shift15 => "0 ps",
|
||||
phase_shift16 => "0 ps",
|
||||
phase_shift17 => "0 ps",
|
||||
phase_shift2 => "0 ps",
|
||||
phase_shift3 => "0 ps",
|
||||
phase_shift4 => "0 ps",
|
||||
phase_shift5 => "0 ps",
|
||||
phase_shift6 => "0 ps",
|
||||
phase_shift7 => "0 ps",
|
||||
phase_shift8 => "0 ps",
|
||||
phase_shift9 => "0 ps",
|
||||
pll_auto_clk_sw_en => "false",
|
||||
pll_bw_sel => "low",
|
||||
pll_bwctrl => 0,
|
||||
pll_clk_loss_sw_en => "false",
|
||||
pll_clk_sw_dly => 0,
|
||||
pll_clkin_0_src => "clk_0",
|
||||
pll_clkin_1_src => "clk_0",
|
||||
pll_cp_current => 0,
|
||||
pll_dsm_out_sel => "1st_order",
|
||||
pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
|
||||
pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
|
||||
pll_fbclk_mux_1 => "glb",
|
||||
pll_fbclk_mux_2 => "fb_1",
|
||||
pll_fractional_cout => 24,
|
||||
pll_fractional_division => 1,
|
||||
pll_m_cnt_in_src => "ph_mux_clk",
|
||||
pll_manu_clk_sw_en => "false",
|
||||
pll_output_clk_frequency => "0 MHz",
|
||||
pll_slf_rst => "false",
|
||||
pll_subtype => "General",
|
||||
pll_type => "General",
|
||||
pll_vco_div => 1,
|
||||
pll_vcoph_div => 1,
|
||||
refclk1_frequency => "0 MHz",
|
||||
reference_clock_frequency => "50.0 MHz",
|
||||
sim_additional_refclk_cycles_to_lock => 0
|
||||
)
|
||||
PORT MAP (
|
||||
fbclk => wire_gnd,
|
||||
locked => wire_pll_main_altera_pll_altera_pll_i_639_locked,
|
||||
outclk => wire_pll_main_altera_pll_altera_pll_i_639_outclk,
|
||||
refclk => refclk,
|
||||
rst => rst
|
||||
);
|
||||
|
||||
END RTL; --pll_main
|
||||
--synopsys translate_on
|
||||
--VALID FILE
|
||||
@@ -0,0 +1,12 @@
|
||||
|
||||
WORK > DEFAULT
|
||||
DEFAULT: ./libraries/work/
|
||||
work: ./libraries/work/
|
||||
altera: ./libraries/altera/
|
||||
lpm: ./libraries/lpm/
|
||||
sgate: ./libraries/sgate/
|
||||
altera_mf: ./libraries/altera_mf/
|
||||
altera_lnsim: ./libraries/altera_lnsim/
|
||||
cyclonev: ./libraries/cyclonev/
|
||||
cyclonev_hssi: ./libraries/cyclonev_hssi/
|
||||
LIBRARY_SCAN = TRUE
|
||||
@@ -0,0 +1,202 @@
|
||||
|
||||
# (C) 2001-2022 Altera Corporation. All rights reserved.
|
||||
# Your use of Altera Corporation's design tools, logic functions and
|
||||
# other software and tools, and its AMPP partner logic functions, and
|
||||
# any output files any of the foregoing (including device programming
|
||||
# or simulation files), and any associated documentation or information
|
||||
# are expressly subject to the terms and conditions of the Altera
|
||||
# Program License Subscription Agreement, Altera MegaCore Function
|
||||
# License Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by Altera
|
||||
# or its authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
|
||||
# ACDS 21.1 850 linux 2022.08.29.18:38:18
|
||||
|
||||
# ----------------------------------------
|
||||
# vcsmx - auto-generated simulation script
|
||||
|
||||
# ----------------------------------------
|
||||
# This script provides commands to simulate the following IP detected in
|
||||
# your Quartus project:
|
||||
# pll_main
|
||||
#
|
||||
# Altera recommends that you source this Quartus-generated IP simulation
|
||||
# script from your own customized top-level script, and avoid editing this
|
||||
# generated script.
|
||||
#
|
||||
# To write a top-level shell script that compiles Altera simulation libraries
|
||||
# and the Quartus-generated IP in your project, along with your design and
|
||||
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
|
||||
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
|
||||
#
|
||||
# You can also modify the simulation flow to suit your needs. Set the
|
||||
# following variables to 1 to disable their corresponding processes:
|
||||
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
|
||||
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
|
||||
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
|
||||
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
|
||||
#
|
||||
# ----------------------------------------
|
||||
# # TOP-LEVEL TEMPLATE - BEGIN
|
||||
# #
|
||||
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
|
||||
# # construct paths to the files required to simulate the IP in your Quartus
|
||||
# # project. By default, the IP script assumes that you are launching the
|
||||
# # simulator from the IP script location. If launching from another
|
||||
# # location, set QSYS_SIMDIR to the output directory you specified when you
|
||||
# # generated the IP script, relative to the directory from which you launch
|
||||
# # the simulator. In this case, you must also copy the generated library
|
||||
# # setup "synopsys_sim.setup" into the location from which you launch the
|
||||
# # simulator, or incorporate into any existing library setup.
|
||||
# #
|
||||
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
|
||||
# # simulation libraries and Quartus-generated IP simulation files, and copy
|
||||
# # any ROM/RAM initialization files to the simulation directory.
|
||||
# #
|
||||
# # - If necessary, specify any compilation options:
|
||||
# # USER_DEFINED_COMPILE_OPTIONS
|
||||
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
|
||||
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_ELAB=1 \
|
||||
# SKIP_SIM=1 \
|
||||
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
|
||||
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
|
||||
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
|
||||
# QSYS_SIMDIR=<script generation output directory>
|
||||
# #
|
||||
# # Compile all design files and testbench files, including the top level.
|
||||
# # (These are all the files required for simulation other than the files
|
||||
# # compiled by the IP script)
|
||||
# #
|
||||
# vlogan <compilation options> <design and testbench files>
|
||||
# #
|
||||
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
|
||||
# # testbench module/entity name.
|
||||
# #
|
||||
# # Run the IP script again to elaborate and simulate the top level:
|
||||
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
|
||||
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
|
||||
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
|
||||
# #
|
||||
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
|
||||
# SKIP_FILE_COPY=1 \
|
||||
# SKIP_DEV_COM=1 \
|
||||
# SKIP_COM=1 \
|
||||
# TOP_LEVEL_NAME="'-top <simulation top>'" \
|
||||
# QSYS_SIMDIR=<script generation output directory> \
|
||||
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
|
||||
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
|
||||
# #
|
||||
# # TOP-LEVEL TEMPLATE - END
|
||||
# ----------------------------------------
|
||||
#
|
||||
# IP SIMULATION SCRIPT
|
||||
# ----------------------------------------
|
||||
# If pll_main is one of several IP cores in your
|
||||
# Quartus project, you can generate a simulation script
|
||||
# suitable for inclusion in your top-level simulation
|
||||
# script by running the following command line:
|
||||
#
|
||||
# ip-setup-simulation --quartus-project=<quartus project>
|
||||
#
|
||||
# ip-setup-simulation will discover the Altera IP
|
||||
# within the Quartus project, and generate a unified
|
||||
# script which supports all the Altera IP within the design.
|
||||
# ----------------------------------------
|
||||
# ACDS 21.1 850 linux 2022.08.29.18:38:18
|
||||
# ----------------------------------------
|
||||
# initialize variables
|
||||
TOP_LEVEL_NAME="pll_main"
|
||||
QSYS_SIMDIR="./../../"
|
||||
QUARTUS_INSTALL_DIR="/datadisk/opt/quartus-lite-21.1.1/quartus/"
|
||||
SKIP_FILE_COPY=0
|
||||
SKIP_DEV_COM=0
|
||||
SKIP_COM=0
|
||||
SKIP_ELAB=0
|
||||
SKIP_SIM=0
|
||||
USER_DEFINED_ELAB_OPTIONS=""
|
||||
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
|
||||
|
||||
# ----------------------------------------
|
||||
# overwrite variables - DO NOT MODIFY!
|
||||
# This block evaluates each command line argument, typically used for
|
||||
# overwriting variables. An example usage:
|
||||
# sh <simulator>_setup.sh SKIP_SIM=1
|
||||
for expression in "$@"; do
|
||||
eval $expression
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
|
||||
exit $?
|
||||
fi
|
||||
done
|
||||
|
||||
# ----------------------------------------
|
||||
# initialize simulation properties - DO NOT MODIFY!
|
||||
ELAB_OPTIONS=""
|
||||
SIM_OPTIONS=""
|
||||
if [[ `vcs -platform` != *"amd64"* ]]; then
|
||||
:
|
||||
else
|
||||
:
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# create compilation libraries
|
||||
mkdir -p ./libraries/work/
|
||||
mkdir -p ./libraries/altera/
|
||||
mkdir -p ./libraries/lpm/
|
||||
mkdir -p ./libraries/sgate/
|
||||
mkdir -p ./libraries/altera_mf/
|
||||
mkdir -p ./libraries/altera_lnsim/
|
||||
mkdir -p ./libraries/cyclonev/
|
||||
mkdir -p ./libraries/cyclonev_hssi/
|
||||
|
||||
# ----------------------------------------
|
||||
# copy RAM/ROM files to simulation directory
|
||||
|
||||
# ----------------------------------------
|
||||
# compile device library files
|
||||
if [ $SKIP_DEV_COM -eq 0 ]; then
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
|
||||
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd" -work cyclonev_hssi
|
||||
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
|
||||
vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd" -work cyclonev_hssi
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# compile design files in correct order
|
||||
if [ $SKIP_COM -eq 0 ]; then
|
||||
vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# elaborate top level design
|
||||
if [ $SKIP_ELAB -eq 0 ]; then
|
||||
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
|
||||
fi
|
||||
|
||||
# ----------------------------------------
|
||||
# simulate
|
||||
if [ $SKIP_SIM -eq 0 ]; then
|
||||
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
|
||||
fi
|
||||
Reference in New Issue
Block a user