47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
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//------------------------------------------------------
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//
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// File : Timer.sv
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// Related Files :
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// Author(s) :
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// Email :
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// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
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// Notes :
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//
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//------------------------------------------------------
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// History
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//------------------------------------------------------
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// Version| Author | Mod. Date | Changes Made:
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// v1.00 | | 11.05.2023 |
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//------------------------------------------------------
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//eoh
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module timer(bus.timer_port fpga_bus, clock_if.clock_port_top c); // (bus.timer b, clock_if.clock_port_top i)
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integer counter = 0; // internal count reg
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integer reload_val;
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always @ (posedge c.clk or fpga_bus.dip[0]) begin
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if (!fpga_bus.dip[0]) begin
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counter <= 0;
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fpga_bus.timer <= 0;
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end else begin
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if(counter <= 800) begin // zu testzwecken kürzer 1000000
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counter++;
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fpga_bus.timer <= 0;
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end else begin
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counter <= 0;
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fpga_bus.timer <= 1;
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end
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end
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end
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//give the input clock on the bus
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always@(posedge c.clk or negedge c.clk)
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fpga_bus.clk = c.clk;
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endmodule : timer
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