42 lines
1.2 KiB
Systemverilog
42 lines
1.2 KiB
Systemverilog
//------------------------------------------------------
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//
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// File : Timer.sv
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// Related Files :
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// Author(s) :
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// Email :
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// Organization : Georg-Simon-Ohm-Hochschule Nuernberg
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// Notes :
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//
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//------------------------------------------------------
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// History
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//------------------------------------------------------
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// Version| Author | Mod. Date | Changes Made:
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// v1.00 | | 11.05.2023 |
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//------------------------------------------------------
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//eoh
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module timer (bus_e bus); // (bus.timer b, clock_if.clock_port_top i)
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integer counter = 0; // internal count reg
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integer reload_val;
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always @ (posedge bus.clk or bus.reset) begin // b.dip[0] <---- soll reset sein i.clk <-- busclk
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if (!bus.reset) begin
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counter <= 0;
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bus.out_10s <= 0; // b.timer <--- out_10s
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end else begin
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if(counter <= 100) begin // zu testzwecken kürzer 1000000
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counter++;
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bus.out_10s <= 0;
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end else begin
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counter <= 0;
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bus.out_10s <= 1;
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end
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end
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end
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endmodule : timer
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