84 lines
1.8 KiB
Systemverilog
84 lines
1.8 KiB
Systemverilog
`include "FRAM_Controller.sv"
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module spi(bus.spi_port b, fram_if.fram_port_top i);
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parameter ringbuffer_size = 256;
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logic [19:0] FRAM_Adr;
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logic [7:0] FRAM_DATA_OUT;
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logic [7:0] FRAM_DATA_IN;
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logic FRAM_RW;
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logic FRAM_RSTATUS;
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logic FRAM_hbn;
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logic FRAM_go;
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logic FRAM_busy;
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logic [7:0] clk_cntr;
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initial begin
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FRAM_Adr <= 20'h0;
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FRAM_DATA_IN <= 8'h0;
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FRAM_RW = 0;
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FRAM_RSTATUS = 0;
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FRAM_hbn = 0;
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FRAM_go = 0;
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clk_cntr = 0;
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end
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always @ (posedge b.timer) begin
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if(b.dip[0] == 0) begin //Reset
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FRAM_Adr <= 20'h0;
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FRAM_DATA_IN <= 8'h0;
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FRAM_RW = 0;
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FRAM_RSTATUS = 0;
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FRAM_hbn = 0;
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FRAM_go = 0;
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clk_cntr = 0;
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end
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else if(b.dip[1] == 1) begin //Read
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FRAM_Adr <= (FRAM_Adr - 1) % (ringbuffer_size - 1);
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FRAM_RW <= 1'h1; //Read
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FRAM_go <= 1'h1; //Go
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end
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else if(b.dip[1] == 0) begin //Write
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FRAM_Adr <= (FRAM_Adr + 1) % (ringbuffer_size - 1);
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FRAM_DATA_IN <= {6'h0, b.dip[4:3]};
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FRAM_RW <= 1'h0; //Write Operation
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FRAM_go <= 1'h1; //Go
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end
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end
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always @ (posedge b.oszi_clk) begin
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if(FRAM_go == 1)
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clk_cntr <= clk_cntr + 1;
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if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
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b.spi_read <= FRAM_DATA_OUT[1:0];
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FRAM_go <= 1'h0;
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FRAM_RW <= 1'h0;
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clk_cntr <= 0;
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end
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else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
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FRAM_go <= 1'h0;
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clk_cntr <= 0;
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end
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end
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FRAM FRAM_ut(
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.i_clk(b.oszi_clk),
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.i_nreset(b.dip[0]),
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.i_adr(FRAM_Adr),
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.i_data(FRAM_DATA_IN),
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.o_data(FRAM_DATA_OUT),
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.i_rw(FRAM_RW),
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.i_status(FRAM_RSTATUS),
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.i_hbn(FRAM_hbn),
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.i_cready(FRAM_go),
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.o_busy(FRAM_busy),
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.o_SPI_Clk(i.sclk),
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.i_SPI_MISO(i.mosi),
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.o_SPI_MOSI(i.mosi),
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.o_SPI_CS_n(i.ss)
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);
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endmodule |