110 lines
3.6 KiB
Systemverilog
110 lines
3.6 KiB
Systemverilog
// Definition of top level
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module top(led_if.led_port_top l, dip_if.dip_port_top d, fram_if.fram_port_top f, clock_if.clock_port_top c);
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// Initialisation of bus
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bus fpga_bus();
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// Initialisation of modules
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timer t(fpga_bus, c);
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steuerung st(fpga_bus, l);
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spi s(fpga_bus, f);
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parallelport p(fpga_bus, d);
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endmodule : top
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// Definition of bus interface
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interface bus();
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// bus wires
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logic clk; // clock
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logic timer;
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logic [3:0]dip;
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logic [1:0]spi_read;
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// modports from modules pov
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modport timer_port(input dip, output timer, clk); //dip[0]
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modport parallel_port(output dip);
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modport steuerung_port(input dip, timer, clk, spi_read); //dip[3:0] / spi_read[1:0]
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modport spi_port(input dip, timer, clk, output spi_read); //spi_read[1:0]
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endinterface : bus
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// Definition of parallelport
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module parallelport(bus.parallel_port b, dip_if.dip_port_top d);
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//b.dip <= d.dip;
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endmodule
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module spi(bus.spi_port b, fram_if.fram_port_top i);
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/*...
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b.dip[3:0], b.timer, b.spi_read[1:0]
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i.ss, i.mosi, i.miso, i.sclk
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...*/
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endmodule
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module timer(bus.timer_port b, clock_if.clock_port_top i);
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/*...
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b.clk, b.dip[0], b.timer
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i.clk
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...*/
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endmodule
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module steuerung(bus.steuerung_port b, led_if.led_port_top i);
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/*...
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b.dip[3:0], b.timer, b.spi_read[1:0]
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i.rgb[2:0]
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...*/
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endmodule
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/*
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_______________________________________________________________________________________________________________
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Testbench
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__________________ ___________________
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| DIP-Schalter | | FRAM-Speicher |
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|__________________| |___________________|
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____________________________|________________________________________________________________|_________________
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Toplevel | |
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dip[3:0]-->| |<--mosi, miso, sclk, ss
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________|_________ ________|__________
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| Parallelport | | SPI-Schnittstelle |
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| | | & FRAM-Kontroller |
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|__________________| |___________________|
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dip[3:0]-->| |<--dip[3:0], timer, spi_read[1:0]
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---------------------------------------------------------------------BUS
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dip[0], clk, timer-->| |<--dip[3:0], timer, spi_read[1:0]
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________|_________ ___________________ ________|__________
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| Timer | | Oszillator-Takt | | Ampel-Steuerung |
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| | | (auf Board) | | |
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|__________________| |___________________| |___________________|
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clk-->------------------------------ |<--rgb[2:0]
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____________________________|________________________________________________________________|___________________
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________|_________ ________|__________
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| Takt | | RGB-LED |
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| (der Testbench) | | |
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|__________________| |___________________|
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__________________________________________________________________________________________________________________
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*/
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