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testbench.sv 3.5KB

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  1. module testbench();
  2. logic clk;
  3. logic nReset;
  4. logic [19:0] FRAM_Adr;
  5. logic [7:0] FRAM_DATA_OUT;
  6. logic [7:0] FRAM_DATA_IN;
  7. logic FRAM_RW;
  8. logic FRAM_RSTATUS;
  9. logic FRAM_hbn;
  10. logic FRAM_go;
  11. logic FRAM_busy;
  12. logic SPI_CLK;
  13. logic SPI_MISO;
  14. logic SPI_MOSI;
  15. logic SPI_CS;
  16. logic [2:0]test;
  17. logic test_running;
  18. logic starttesting;
  19. localparam TESTS_cnt = 5;
  20. initial begin
  21. // Required for EDA Playground
  22. $dumpfile("dump.vcd");
  23. $dumpvars;
  24. clk = 1'h0;
  25. nReset = 1'h0;
  26. FRAM_Adr <= 20'h0;
  27. FRAM_DATA_IN <= 8'h0;
  28. FRAM_RW = 0;
  29. FRAM_RSTATUS = 0;
  30. FRAM_hbn = 0;
  31. FRAM_go = 0;
  32. test <= 2'h0;
  33. repeat(10) @(posedge clk);
  34. nReset = 1'h1;
  35. starttesting <= 1'h1;
  36. test_running <= 1'h0;
  37. end //initial end
  38. // Clock Generation:
  39. always #(5) clk = ~clk; //clk 100MHz
  40. // end Clock Generation
  41. always @ (posedge starttesting or posedge FRAM_busy) begin
  42. repeat(10) @(posedge clk);
  43. if(test_running == 1'h0 & FRAM_busy == 1'h1) begin
  44. if(test == TESTS_cnt+1) begin
  45. test_running <= 1'h0;
  46. $display("Tests Finished");
  47. $finish;
  48. end
  49. case(test) inside
  50. 3'b000: begin Test1(); test <= test + 1'h1; end
  51. 3'b001: begin Test2(); test <= test + 1'h1; end
  52. 3'b010: begin Test3(); test <= test + 1'h1; end
  53. 3'b011: begin Test4(); test <= test + 1'h1; end
  54. endcase
  55. end // endif
  56. end // end always
  57. task Test1();
  58. test_running <= 1'h1;
  59. $display("DEBUG: %0tns: Test_1_Hibernation",$realtime);
  60. FRAM_hbn <= 1'h1; //Enter Hibernation
  61. FRAM_go <= 1'h1;
  62. #10;
  63. FRAM_hbn <= 1'h0; //Reset Hibernation Flag
  64. FRAM_go <= 1'h0;
  65. $display("DEBUG: %0tns: Test_1_Hibernation__-END",$realtime);
  66. test_running <= 1'h0;
  67. endtask
  68. task Test2();
  69. test_running <= 1'h1;
  70. $display("DEBUG: %0tns: Test_2_ReadStatus",$realtime);
  71. FRAM_RSTATUS <= 1'h1; //Read Status
  72. FRAM_go <= 1'h1; //Go
  73. #10;
  74. FRAM_RSTATUS <= 1'h0; //Read Status
  75. FRAM_go <= 1'h0; //reset Go
  76. $display("DEBUG: %0tns: Test_2_ReadStatus__-END",$realtime);
  77. test_running <= 1'h0;
  78. endtask
  79. task Test3();
  80. test_running <= 1'h1;
  81. $display("DEBUG: %0tns: Test_3_FRAM_WRITE",$realtime);
  82. FRAM_Adr <= 20'h8FFF1; //Load 8FFF1 as adress
  83. FRAM_DATA_IN <= 8'hAA; //Load AA as Data to Write into FRAM
  84. FRAM_RW <= 1'h0; //Write Operation
  85. FRAM_go <= 1'h1; //Go
  86. #10;
  87. FRAM_go <= 1'h0; //resetGo
  88. $display("DEBUG: %0tns: Test_3_FRAM_WRITE__-END",$realtime);
  89. test_running <= 1'h0;
  90. endtask
  91. task Test4();
  92. test_running <= 1'h1;
  93. $display("DEBUG: %0tns: Test_4_FRAM_READ",$realtime);
  94. FRAM_Adr <= 20'h8FFF1; //Load 8FFF1 as adress
  95. FRAM_RW <= 1'h1; //Read
  96. FRAM_go <= 1'h1; //Go
  97. #10;
  98. FRAM_go <= 1'h0; //resetGo
  99. FRAM_RW <= 1'h0; //Read
  100. $display("DEBUG: %0tns: Test_4_FRAM_READ__-END",$realtime);
  101. test_running <= 1'h0;
  102. endtask
  103. FRAM FRAM_ut(
  104. .i_clk(clk),
  105. .i_nreset(nReset),
  106. .i_adr(FRAM_Adr),
  107. .i_data(FRAM_DATA_IN),
  108. .o_data(FRAM_DATA_OUT),
  109. .i_rw(FRAM_RW),
  110. .i_status(FRAM_RSTATUS),
  111. .i_hbn(FRAM_hbn),
  112. .i_cready(FRAM_go),
  113. .o_busy(FRAM_busy),
  114. .o_SPI_Clk(SPI_CLK),
  115. .i_SPI_MISO(SPI_MOSI), // !!! only for Testing!!!
  116. .o_SPI_MOSI(SPI_MOSI), //
  117. .o_SPI_CS_n(SPI_CS)
  118. );
  119. endmodule