library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

-- tbd
-- if _read is 1 _readdata is read
-- if _write is 1 _writedata is written
-- float_add instanziieren


-- state machine that sets taskState and write signals
architecture rtl of add is

	component float_add
	port (
		clk : in std_logic;
		reset : in std_logic;
		start : in std_logic;
		A : in std_logic_vector( 31 downto 0 );
		B : in std_logic_vector( 31 downto 0 );
		done : out std_logic;
		sum : out std_logic_vector( 31 downto 0 )
		);
	end component float_add;

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
	
	signal float_add_start : std_logic;
	signal float_add_A : std_logic_vector( 31 downto 0 );
	signal float_add_B : std_logic_vector( 31 downto 0 );
	signal float_add_done :  std_logic;
	signal float_add_sum : std_logic_vector( 31 downto 0 );

	signal add_state : integer range 0 to 3;
	signal flag_index : bit;


begin

	float_adder : float_add
	port map (
		clk => clk,
		reset => reset,
		start => float_add_start,
		A => float_add_A,		-- feed readdata into float adder
		B => float_add_B,		-- feed readdata into float adder
		done => float_add_done,		-- write signal when float addition is finished
		sum => float_add_sum		-- feed output of float adder into writedata
		);

    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
--                signal_write <= '0';
            when work.task.TASK_RUNNING => -- signal_writedata <= result???
				if ( flag_index = '1' ) then
					index <= index + 1;
				end if;
--                signal_write <= '1';
--                signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                index <= 0;
--                signal_write <= '0';
            end case;
        end if;
    end process sync;

	add : process (clk, reset) is
	begin
		if ( reset = '1' ) then
            signal_a_read <= '0';
			signal_b_read <= '0';
			signal_write <= '0';
			signal_writedata <= ( others => '0');
			float_add_start <= '0';
			float_add_A <= ( others => '0');
			float_add_B <= ( others => '0');
        elsif ( rising_edge( clk ) ) then
			case add_state is
			when 0 =>
				if ( current_task_state = work.task.TASK_RUNNING ) then
					add_state <= 1;
				end if;
			when 1 =>
				signal_a_read <= '1';
				signal_b_read <= '1';
				float_add_start <= '1';
				float_add_A <= signal_a_readdata;
				float_add_B <= signal_b_readdata;
				if ( float_add_done = '1' ) then
					add_state <= 2;
				end if;
			when 2 =>
				signal_write <= '1';
				signal_writedata <= float_add_sum;
				float_add_start <= '0';
				signal_a_read <= '0';
				signal_b_read <= '0';
				flag_index <= '1';
				add_state <= 3;
			when 3 =>
				signal_write <= '0';
				flag_index <= '0';
				add_state <= 0;
			end case;
		end if;
	end process add;

    task_state <= current_task_state;

end architecture rtl;