signal_processing_vorlage/hardware/system/sync_ff.vhd

library ieee;
    use ieee.std_logic_1164.all;

entity sync_ff is
    generic
    (
        DEPTH     : positive range 2 to 5 := 2;
        RST_VALUE : std_logic             := '0'
    );

    port
    (
        --! Destination domain clock
        clk    : in  std_logic;
        --! Low active destination domain reset
        reset  : in  std_logic;

        --! Single bit data input
        din    : in  std_logic;
        --! Single bit data output
        dout   : out std_logic
    );

end entity sync_ff;

architecture rtl of sync_ff is

    signal sync : std_logic_vector( DEPTH - 1 downto 0 );

begin

    p_sync: process ( clk, reset ) is
    begin

        if ( reset = '1' ) then

	    sync <= ( others => RST_VALUE );

	elsif ( rising_edge( clk ) ) then

            sync( DEPTH - 1 downto 1 ) <= sync( DEPTH - 2 downto 0 );
            sync( 0 )                  <= din;

        end if;
    end process p_sync;

    c_dout:   dout                       <= sync( DEPTH - 1 );

end architecture rtl;