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This commit is contained in:
Johannes Kutning
2023-10-31 07:47:27 +01:00
commit 0d1b73e3e0
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tests/hardware/data_tests.mk
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artifacts += data.py __pycache__
CHECK_RESULTS = true
include ../vhdl.mk
plot: CHECK_RESULTS = false
plot: sim
@echo Plotting resulting signal vs. expected signal ...
@../../scripts/plot.py ${expected_data} 2> /dev/null
tests/hardware/ghdl.mk
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#
#
#
#
# Make sure that the top level is assigned to main
$(if $(main),,\
$(error Assign top level entity name to variable "main"))
# Make sure that at least on vhdl source is assigned
$(if $(vhdl_srcs),,\
$(error Assign at least on vhdl source to variable "vhdl_srcs"))
# Append prefix -d to all generics
generics = $(addprefix -g,$(generics))
# Add VHDL 2008 as default build standard
vhdl_flags += --std=08
vhdl_objs = $(vhdl_srcs:.vhd=.o)
assert_level := error
.PHONY: sim clean
sim: ${main}
@../../scripts/execute_and_highlight.sh ghdl -r ${vhdl_flags} ${main} -gCHECK_RESULTS=${CHECK_RESULTS} \
--read-wave-opt=${main}.wave \
--assert-level=${assert_level}
gui: ${main}.ghw
@echo "Viewing $<"
@gtkwave $< --script=gtkwave.view
${main}.ghw: ${main} ${main}.wave
@ghdl -r ${vhdl_flags} ${main} \
--read-wave-opt=${main}.wave \
--wave=$@
${main}: $(vhdl_objs)
@echo "Elaborating ${main}"
@ghdl -e ${vhdl_flags} ${main}
%.o: %.vhd
@echo "Analysing $<"
@ghdl -a ${vhdl_flags} $<
clean:
@ghdl --clean
@rm -rf ${main}.ghw work-obj08.cf ${vhdl_objs} ${main} ${artifacts}
help:
@echo Use ghdl to simulate and synthesis a vhdl design.
@echo
@echo Build configuration variables:
@echo main main entity
@echo vhdl_flags
@echo generics
tests/hardware/questa-sim.mk
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#
#
#
#
# Make sure that the top level is assigned to main
$(if $(main),,\
$(error Assign top level entity name to variable "main"))
# Make sure that at least on vhdl source is assigned
$(if $(vhdl_srcs),,\
$(error Assign at least on vhdl source to variable "vhdl_srcs"))
# Append prefix -d to all generics
generics = $(addprefix -g,$(generics))
# Add VHDL 2008 as default build standard
vhdl_flags += -2008
vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
verilog_objs = $(verilog_srcs:.v=.vo)
assert_level := error
.PHONY: sim clean
sim: ${verilog_objs} ${vhdl_objs}
@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -voptargs=+acc -c work.${main} -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" \
| ../../scripts/highlight_test_results.sh
gui: ${verilog_objs} ${vhdl_objs}
@vsim -gCHECK_RESULTS=${CHECK_RESULTS} -gGUI_MODE=true -voptargs=+acc work.${main} -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all"
%.vo: %.v .libwork
@echo "Analysing $<"
@vlog -work work ${verilog_flags} $<
%.vhdo: %.vhd .libwork
@echo "Analysing $<"
@vcom -work work ${vhdl_flags} $<
.libwork:
@vlib work && vmap work work && touch $@
clean:
@rm -rf work \
.libwork \
transcript \
modelsim.ini \
vlog.opt \
vsim.wlf \
data.py \
data.pyc \
help:
@echo Use ghdl to simulate and synthesis a vhdl design.
@echo
@echo Build configuration variables:
@echo main main entity
@echo vhdl_flags
@echo generics
tests/hardware/task_add_rand/Makefile
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vhdl_srcs = ../../../hardware/system/reg32.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/avalon_slave.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/float_add.vhd \
../../../hardware/signal_processing/add.vhd \
../../../hardware/system/task_add.vhd \
../../../hardware/system/data_channel_control.vhd \
../../../hardware/system/data_sink_mux.vhd \
../../../hardware/system/data_source_mux.vhd \
../../../hardware/system/fifo.vhd \
../../../hardware/system/data_channel.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../test_data_channel.vhd \
../../data/sine_cosine.vhd \
../../data/rand.vhd \
../../data/add_rand.vhd \
test_task_add_rand.vhd \
main = test_task_add_rand
expected_data = ../../data/add_rand.py
include ../data_tests.mk
tests/hardware/task_add_rand/test_task_add_rand.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
use work.test_utility.all;
use work.test_avalon_slave.all;
use work.task.all;
use work.test_hardware_task.all;
use work.test_data_channel_pkg.all;
library std;
use std.env.all;
use std.textio.all;
entity test_task_add_rand is
generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
end entity test_task_add_rand;
architecture test of test_task_add_rand is
procedure test_configure( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable index : integer := 0;
variable writedata : std_logic_vector( 31 downto 0 );
begin
std.textio.write( std.textio.OUTPUT, " test_configure ... " );
index := 0;
writedata := x"08000000"; -- 2^32 / 32
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 1;
writedata := x"00000000";
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 2;
writedata := x"40800000"; -- 2 ** 2 = 4 float
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_configure;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal req : work.avalon_slave.Request;
signal rsp : work.avalon_slave.Response;
signal data_channel_req : work.avalon_slave.Request;
signal data_channel_rsp : work.avalon_slave.Response;
signal signal_a_read : std_logic;
signal signal_a_readdata : std_logic_vector( 31 downto 0 );
signal signal_b_read : std_logic;
signal signal_b_readdata : std_logic_vector( 31 downto 0 );
signal signal_write : std_logic;
signal signal_writedata : std_logic_vector( 31 downto 0 );
signal data_channel_read : std_logic;
signal data_channel_readdata : std_logic_vector( 31 downto 0 );
begin
dut : entity work.task_add
port map (
clk => clk,
reset => reset,
address => req.address,
read => req.read,
readdata => rsp.readdata,
write => req.write,
writedata => req.writedata,
signal_a_read => signal_a_read,
signal_a_readdata => signal_a_readdata,
signal_b_read => signal_b_read,
signal_b_readdata => signal_b_readdata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
u_data_channel : entity work.data_channel
port map (
clk => clk,
reset => reset,
ctrl_address => data_channel_req.address,
ctrl_read => data_channel_req.read,
ctrl_readdata => data_channel_rsp.readdata,
ctrl_write => data_channel_req.write,
ctrl_writedata => data_channel_req.writedata,
hw_sink_write => signal_write,
hw_sink_writedata => signal_writedata,
hw_source_read => data_channel_read,
hw_source_readdata => data_channel_readdata
);
clk <= not clk after 10 ns;
reset_release : process is
begin
wait for 35 ns;
reset <= '0';
wait;
end process reset_release;
input_data_a_simulus: process is
variable index : integer := 0;
begin
while true loop
signal_a_readdata <= to_std_logic_vector( to_float( work.sine_cosine_data.expected( index ) ) );
wait until rising_edge( signal_a_read );
if ( index < 1023 ) then
index := index + 1;
end if;
end loop;
end process input_data_a_simulus;
input_data_b_simulus: process is
variable index : integer := 0;
begin
while true loop
signal_b_readdata <= to_std_logic_vector( to_float( work.rand_data.expected( index ) ) );
wait until rising_edge( signal_b_read );
if ( index < 1023 ) then
index := index + 1;
end if;
end loop;
end process input_data_b_simulus;
stimulus: process is
variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );
std.textio.write( std.textio.OUTPUT, "Starting test_task_add_rand" & LF );
wait until falling_edge( reset );
wait until falling_edge( clk );
work.test_data_channel_pkg.write_and_assert_config( clk => clk,
req => data_channel_req,
rsp => data_channel_rsp,
config => data_channel_config );
test_configure( clk => clk, req => req, rsp => rsp );
test_execute( clk => clk, req => req, rsp => rsp,
write => signal_write, writedata => signal_writedata );
for i in 0 to 10 loop
wait until falling_edge( clk );
end loop;
if ( CHECK_RESULTS ) then
check_and_write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp,
expected => work.add_rand_data.expected );
else
write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp );
end if;
if ( GUI_MODE ) then
std.env.stop;
else
std.env.finish;
end if;
end process stimulus;
end architecture test;
tests/hardware/task_add_rand/test_task_add_rand.wave
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$ version 1.1
/test_task_add_sine_cosine/*
/test_task_add_sine_cosine/dut/*
/test_task_add_sine_cosine/dut/u_add/*
/test_task_add_sine_cosine/dut/u_add/u_float_add/*
tests/hardware/task_add_rand/vsim.wave
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add wave -position end sim:/test_task_add_rand/dut/u_add/*
tests/hardware/task_add_sine_cosine/Makefile
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vhdl_srcs = ../../../hardware/system/reg32.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/avalon_slave.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/float_add.vhd \
../../../hardware/signal_processing/add.vhd \
../../../hardware/system/task_add.vhd \
../../../hardware/system/data_channel_control.vhd \
../../../hardware/system/data_sink_mux.vhd \
../../../hardware/system/data_source_mux.vhd \
../../../hardware/system/fifo.vhd \
../../../hardware/system/data_channel.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../test_data_channel.vhd \
../../data/sine.vhd \
../../data/cosine.vhd \
../../data/sine_cosine.vhd \
test_task_add_sine_cosine.vhd \
main = test_task_add_sine_cosine
expected_data = ../../data/sine_cosine.py
include ../data_tests.mk
tests/hardware/task_add_sine_cosine/test_task_add_sine_cosine.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
use work.test_utility.all;
use work.test_avalon_slave.all;
use work.task.all;
use work.sine_data.all;
use work.test_hardware_task.all;
use work.test_data_channel_pkg.all;
library std;
use std.env.all;
use std.textio.all;
entity test_task_add_sine_cosine is
generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
end entity test_task_add_sine_cosine;
architecture test of test_task_add_sine_cosine is
procedure test_configure( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable index : integer := 0;
variable writedata : std_logic_vector( 31 downto 0 );
begin
std.textio.write( std.textio.OUTPUT, " test_configure ... " );
index := 0;
writedata := x"08000000"; -- 2^32 / 32
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 1;
writedata := x"00000000";
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 2;
writedata := x"40800000"; -- 2 ** 2 = 4 float
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_configure;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal req : work.avalon_slave.Request;
signal rsp : work.avalon_slave.Response;
signal data_channel_req : work.avalon_slave.Request;
signal data_channel_rsp : work.avalon_slave.Response;
signal signal_a_read : std_logic;
signal signal_a_readdata : std_logic_vector( 31 downto 0 );
signal signal_b_read : std_logic;
signal signal_b_readdata : std_logic_vector( 31 downto 0 );
signal signal_write : std_logic;
signal signal_writedata : std_logic_vector( 31 downto 0 );
signal data_channel_read : std_logic;
signal data_channel_readdata : std_logic_vector( 31 downto 0 );
begin
dut : entity work.task_add
port map (
clk => clk,
reset => reset,
address => req.address,
read => req.read,
readdata => rsp.readdata,
write => req.write,
writedata => req.writedata,
signal_a_read => signal_a_read,
signal_a_readdata => signal_a_readdata,
signal_b_read => signal_b_read,
signal_b_readdata => signal_b_readdata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
u_data_channel : entity work.data_channel
port map (
clk => clk,
reset => reset,
ctrl_address => data_channel_req.address,
ctrl_read => data_channel_req.read,
ctrl_readdata => data_channel_rsp.readdata,
ctrl_write => data_channel_req.write,
ctrl_writedata => data_channel_req.writedata,
hw_sink_write => signal_write,
hw_sink_writedata => signal_writedata,
hw_source_read => data_channel_read,
hw_source_readdata => data_channel_readdata
);
clk <= not clk after 10 ns;
reset_release : process is
begin
wait for 35 ns;
reset <= '0';
wait;
end process reset_release;
input_data_a_simulus: process is
variable index : integer := 0;
begin
while true loop
signal_a_readdata <= to_std_logic_vector( to_float( work.sine_data.expected( index ) ) );
wait until rising_edge( signal_a_read );
if ( index < 1023 ) then
index := index + 1;
end if;
end loop;
end process input_data_a_simulus;
input_data_b_simulus: process is
variable index : integer := 0;
begin
while true loop
signal_b_readdata <= to_std_logic_vector( to_float( work.cosine_data.expected( index ) ) );
wait until rising_edge( signal_b_read );
if ( index < 1023 ) then
index := index + 1;
end if;
end loop;
end process input_data_b_simulus;
stimulus: process is
variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
std.textio.write( std.textio.OUTPUT, "--------------------------------------------------------------------------------" & LF );
std.textio.write( std.textio.OUTPUT, "Starting test_task_add_sine_cosine" & LF );
wait until falling_edge( reset );
wait until falling_edge( clk );
work.test_data_channel_pkg.write_and_assert_config( clk => clk,
req => data_channel_req,
rsp => data_channel_rsp,
config => data_channel_config );
test_configure( clk => clk, req => req, rsp => rsp );
test_execute( clk => clk, req => req, rsp => rsp,
write => signal_write, writedata => signal_writedata );
for i in 0 to 10 loop
wait until falling_edge( clk );
end loop;
if ( CHECK_RESULTS ) then
check_and_write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp,
expected => work.sine_cosine_data.expected );
else
write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp );
end if;
if ( GUI_MODE ) then
std.env.stop;
else
std.env.finish;
end if;
end process stimulus;
end architecture test;
tests/hardware/task_add_sine_cosine/test_task_add_sine_cosine.wave
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$ version 1.1
/test_task_add_sine_cosine/*
/test_task_add_sine_cosine/dut/*
/test_task_add_sine_cosine/dut/u_add/*
/test_task_add_sine_cosine/dut/u_add/u_float_add/*
/test_task_add_sine_cosine/u_data_channel/**
tests/hardware/task_add_sine_cosine/vsim.wave
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add wave -position end sim:/test_task_add_sine_cosine/dut/u_add/*
tests/hardware/task_cosine/Makefile
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vhdl_srcs = ../../../hardware/system/reg32.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/avalon_slave.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/float.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/data_channel_control.vhd \
../../../hardware/system/data_sink_mux.vhd \
../../../hardware/system/data_source_mux.vhd \
../../../hardware/system/fifo.vhd \
../../../hardware/system/data_channel.vhd \
../../../hardware/system/cordic_pkg.vhd \
../../../hardware/system/cordic.vhd \
../../../hardware/system/fixed_sine.vhd \
../../../hardware/system/float_sine.vhd \
../../../hardware/signal_processing/sine.vhd \
../../../hardware/system/task_sine.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../test_data_channel.vhd \
../../data/cosine.vhd \
test_task_cosine.vhd \
main = test_task_cosine
expected_data = ../../data/cosine.py
include ../data_tests.mk
tests/hardware/task_cosine/test_task_cosine.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
use work.test_utility.all;
use work.test_avalon_slave.all;
use work.task.all;
use work.cosine_data.all;
use work.test_hardware_task.all;
use work.test_data_channel_pkg.all;
library std;
use std.env.all;
use std.textio.all;
entity test_task_cosine is
generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
end entity test_task_cosine;
architecture test of test_task_cosine is
procedure test_configure( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable index : integer := 0;
variable writedata : std_logic_vector( 31 downto 0 );
begin
std.textio.write( std.textio.OUTPUT, " test_configure ... " );
index := 0;
writedata := x"0147ae14"; -- 2^32 / 32
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 1;
writedata := x"40000000";
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 2;
writedata := x"40000000"; -- 2 ** 2 = 4 float
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_configure;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal req : work.avalon_slave.Request;
signal rsp : work.avalon_slave.Response;
signal data_channel_req : work.avalon_slave.Request;
signal data_channel_rsp : work.avalon_slave.Response;
signal signal_write : std_logic;
signal signal_writedata : std_logic_vector( 31 downto 0 );
signal data_channel_read : std_logic;
signal data_channel_readdata : std_logic_vector( 31 downto 0 );
begin
dut : entity work.task_sine
port map (
clk => clk,
reset => reset,
address => req.address,
read => req.read,
readdata => rsp.readdata,
write => req.write,
writedata => req.writedata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
u_data_channel : entity work.data_channel
port map (
clk => clk,
reset => reset,
ctrl_address => data_channel_req.address,
ctrl_read => data_channel_req.read,
ctrl_readdata => data_channel_rsp.readdata,
ctrl_write => data_channel_req.write,
ctrl_writedata => data_channel_req.writedata,
hw_sink_write => signal_write,
hw_sink_writedata => signal_writedata,
hw_source_read => data_channel_read,
hw_source_readdata => data_channel_readdata
);
clk <= not clk after 10 ns;
reset_release : process is
begin
wait for 35 ns;
reset <= '0';
wait;
end process reset_release;
stimulus: process is
variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( reset );
work.test_data_channel_pkg.write_and_assert_config( clk => clk,
req => data_channel_req,
rsp => data_channel_rsp,
config => data_channel_config );
test_configure( clk => clk, req => req, rsp => rsp );
test_execute( clk => clk, req => req, rsp => rsp,
write => signal_write, writedata => signal_writedata );
if ( CHECK_RESULTS ) then
check_and_write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp,
expected => work.cosine_data.expected );
else
write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp );
end if;
if ( GUI_MODE ) then
std.env.stop;
else
std.env.finish;
end if;
end process stimulus;
end architecture test;
tests/hardware/task_cosine/test_task_cosine.wave
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$ version 1.1
/test_task_sine/*
/test_task_sine/dut/*
/test_task_sine/dut/u_sine/*
/test_task_sine/dut/u_sine/u_float_sine/*
/test_task_sine/dut/u_sine/u_float_sine/u_fixed_sine/*
tests/hardware/task_cosine/vsim.wave
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add wave -position end sim:/test_task_cosine/dut/u_sine/*
tests/hardware/task_crc/Makefile
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vhdl_srcs = ../../../hardware/system/reg32.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/avalon_slave.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/float.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/data_channel_control.vhd \
../../../hardware/system/data_sink_mux.vhd \
../../../hardware/system/data_source_mux.vhd \
../../../hardware/system/fifo.vhd \
../../../hardware/system/data_channel.vhd \
../../../hardware/signal_processing/crc.vhd \
../../../hardware/system/task_crc.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../test_data_channel.vhd \
../../data/fft.vhd \
../../data/crc.vhd \
test_task_crc.vhd \
main = test_task_crc
expected_data = ../../data/crc.py
CHECK_RESULTS = true
include ../vhdl.mk
tests/hardware/task_crc/test_task_crc.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
use work.test_utility.all;
use work.test_avalon_slave.all;
use work.task.all;
use work.crc_data.all;
use work.fft_data.all;
use work.test_hardware_task.all;
use work.test_data_channel_pkg.all;
library std;
use std.env.all;
use std.textio.all;
entity test_task_crc is
generic( CHECK_RESULTS : boolean );
end entity test_task_crc;
architecture test of test_task_crc is
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal req : work.avalon_slave.Request;
signal rsp : work.avalon_slave.Response;
signal data_channel_req : work.avalon_slave.Request;
signal data_channel_rsp : work.avalon_slave.Response;
signal signal_read : std_logic;
signal signal_readdata : std_logic_vector( 31 downto 0 );
signal signal_write : std_logic;
signal signal_writedata : std_logic_vector( 31 downto 0 );
signal data_channel_read : std_logic;
signal data_channel_readdata : std_logic_vector( 31 downto 0 );
signal index_output : integer range 0 to 1023;
begin
dut : entity work.task_crc
port map (
clk => clk,
reset => reset,
address => req.address,
read => req.read,
readdata => rsp.readdata,
write => req.write,
writedata => req.writedata,
signal_read => signal_read,
signal_readdata => signal_readdata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
u_data_channel : entity work.data_channel
port map (
clk => clk,
reset => reset,
ctrl_address => data_channel_req.address,
ctrl_read => data_channel_req.read,
ctrl_readdata => data_channel_rsp.readdata,
ctrl_write => data_channel_req.write,
ctrl_writedata => data_channel_req.writedata,
hw_sink_write => signal_write,
hw_sink_writedata => signal_writedata,
hw_source_read => data_channel_read,
hw_source_readdata => data_channel_readdata
);
clk <= not clk after 10 ns;
reset_release : process is
begin
wait for 35 ns;
reset <= '0';
wait;
end process reset_release;
p_number_input_sample: process ( clk, reset ) is
begin
if ( reset = '1' ) then
index_output <= 1;
signal_readdata <= to_std_logic_vector( to_float( work.fft_data.expected( 0 ) ) );
elsif ( rising_edge( clk ) ) then
if signal_read = '1' then
if index_output /= 1023 then
index_output <= index_output + 1;
end if;
signal_readdata <= to_std_logic_vector( to_float( work.fft_data.expected( index_output ) ) );
end if;
end if;
end process p_number_input_sample;
stimulus: process is
variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
variable expected_crc_value : std_logic_vector( 31 downto 0 ) := work.crc_data.expected;
begin
wait until falling_edge( reset );
work.test_data_channel_pkg.write_and_assert_config( clk => clk,
req => data_channel_req,
rsp => data_channel_rsp,
config => data_channel_config );
test_execute( clk => clk, req => req, rsp => rsp,
write => signal_write, writedata => signal_writedata );
std.textio.write( std.textio.OUTPUT, " test_crc_value ... " );
assert_read_sw_source_eq( clk => clk,
req => data_channel_req, rsp => data_channel_rsp,
expected => expected_crc_value );
std.textio.write( std.textio.OUTPUT, TEST_OK );
finish;
end process stimulus;
end architecture test;
tests/hardware/task_crc/test_task_crc.wave
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$ version 1.1
/test_task_crc/*
/test_task_crc/dut/*
tests/hardware/task_crc/vsim.wave
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add wave -position end sim:/test_task_crc/dut/u_crc/*
tests/hardware/task_fft/Makefile
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verilog_srcs = \
../../../hardware/system/Butterfly.v \
../../../hardware/system/DelayBuffer.v \
../../../hardware/system/FFT1024_32B.v \
../../../hardware/system/Multiply.v \
../../../hardware/system/SdfUnit2.v \
../../../hardware/system/SdfUnit.v \
../../../hardware/system/Twiddle1024_32B.v \
vhdl_srcs = \
../../../hardware/system/reg32.vhd \
../../../hardware/system/avalon_slave.vhd \
../../hardware/test_data_channel.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/hardware_task.vhd \
../../../hardware/system/float.vhd \
../../../hardware/system/squareRoot_pipe.vhd \
../../../hardware/system/fft_magnitude_calc.vhd \
../../../hardware/signal_processing/fft.vhd \
../../../hardware/system/task_fft.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../../data/add_rand.vhd \
../../data/sine.vhd \
../../data/fft.vhd \
test_task_fft.vhd \
main = test_task_fft
expected_data = ../../data/fft.py
include ../data_tests.mk
tests/hardware/task_fft/test_task_fft.vhd
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tests/hardware/task_fft/test_task_fft.wave
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$ version 1.1
/test_task_add_sine_cosine/*
/test_task_add_sine_cosine/dut/*
/test_task_add_sine_cosine/dut/u_add/*
/test_task_add_sine_cosine/dut/u_add/u_float_add/*
tests/hardware/task_fft/vsim.wave
+1
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add wave -position end sim:/test_task_fft/dut/*
tests/hardware/task_rand/Makefile
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vhdl_srcs = ../../../hardware/system/reg32.vhd \
../../../hardware/system/avalon_slave.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/data_channel_control.vhd \
../../../hardware/system/data_sink_mux.vhd \
../../../hardware/system/data_source_mux.vhd \
../../../hardware/system/fifo.vhd \
../../../hardware/system/data_channel.vhd \
../../../hardware/signal_processing/rand.vhd \
../../../hardware/system/task_rand.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../test_data_channel.vhd \
../../data/rand.vhd \
test_task_rand.vhd \
main = test_task_rand
expected_data = ../../data/rand.py
include ../data_tests.mk
tests/hardware/task_rand/test_task_rand.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.test_hardware_task.all;
use work.task.all;
use work.rand_data.all;
use work.test_utility.all;
use work.test_data_channel_pkg.all;
library std;
use std.env.all;
use std.textio.all;
entity test_task_rand is
generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
end entity test_task_rand;
architecture test of test_task_rand is
procedure test_configure( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable index : integer := 0;
variable writedata : std_logic_vector( 31 downto 0 );
begin
std.textio.write( std.textio.OUTPUT, " test_configure ... " );
writedata := to_std_logic_vector( to_float( 1.3 ) );
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_configure;
procedure test_execute( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
signal write : in std_logic;
signal writedata : in std_logic_vector( 31 downto 0 )) is
variable expected_readdata : std_logic_vector( 31 downto 0 );
variable state : std_logic_vector( 31 downto 0 );
variable index : integer := 0;
begin
std.textio.write( std.textio.OUTPUT, " test_execute ... " );
expected_readdata := to_std_logic_vector( TASK_IDLE, expected_readdata'length );
assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );
write_start( clk => clk, req => req );
expected_readdata := to_std_logic_vector( TASK_RUNNING, expected_readdata'length );
assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );
while true loop
work.test_hardware_task.read_state( clk => clk, req => req, rsp => rsp, state => state );
if ( state = to_std_logic_vector( TASK_DONE, expected_readdata'length ) ) then
exit;
end if;
end loop;
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_execute;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal req : work.avalon_slave.Request;
signal rsp : work.avalon_slave.Response;
signal data_channel_req : work.avalon_slave.Request;
signal data_channel_rsp : work.avalon_slave.Response;
signal address : std_logic_vector( 3 downto 0 );
signal read : std_logic := '0';
signal readdata : std_logic_vector( 31 downto 0 );
signal write : std_logic := '0';
signal writedata : std_logic_vector( 31 downto 0 );
signal signal_write : std_logic;
signal signal_writedata : std_logic_vector( 31 downto 0 );
signal results : work.reg32.RegArray( 0 to 1023 );
signal data_channel_read : std_logic;
signal data_channel_readdata : std_logic_vector( 31 downto 0 );
begin
dut : entity work.task_rand
port map (
clk => clk,
reset => reset,
address => req.address,
read => req.read,
readdata => rsp.readdata,
write => req.write,
writedata => req.writedata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
u_data_channel : entity work.data_channel
port map (
clk => clk,
reset => reset,
ctrl_address => data_channel_req.address,
ctrl_read => data_channel_req.read,
ctrl_readdata => data_channel_rsp.readdata,
ctrl_write => data_channel_req.write,
ctrl_writedata => data_channel_req.writedata,
hw_sink_write => signal_write,
hw_sink_writedata => signal_writedata,
hw_source_read => data_channel_read,
hw_source_readdata => data_channel_readdata
);
clk <= not clk after 10 ns;
reset_release : process is
begin
wait for 35 ns;
reset <= '0';
wait;
end process reset_release;
stimulus: process is
constant expected : work.reg32.RegArray( 0 to 3 )
:= ( 0 => ( others => 'U' ), 2 => ( others => 'U' ),
others => ( others => '0' ) );
variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( reset );
work.test_data_channel_pkg.write_and_assert_config( clk => clk,
req => data_channel_req,
rsp => data_channel_rsp,
config => data_channel_config );
test_configure( clk => clk, req => req, rsp => rsp );
test_execute( clk => clk, req => req, rsp => rsp,
write => signal_write, writedata => signal_writedata );
if ( CHECK_RESULTS ) then
check_and_write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp,
expected => work.rand_data.expected );
else
write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp );
end if;
if ( GUI_MODE ) then
std.env.stop;
else
std.env.finish;
end if;
end process stimulus;
end architecture test;
tests/hardware/task_rand/test_task_rand.wave
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$ version 1.1
/test_task_rand/*
/test_task_rand/dut/**
/test_task_rand/u_data_channel/**
tests/hardware/task_rand/vsim.wave
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add wave -position end sim:/test_task_rand/dut/u_rand/*
tests/hardware/task_sine/Makefile
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vhdl_srcs = ../../../hardware/system/reg32.vhd \
../../../hardware/system/task.vhd \
../../../hardware/system/avalon_slave.vhd \
../../../hardware/system/avalon_slave_transitions.vhd \
../../../hardware/system/float.vhd \
../../../hardware/system/hardware_task_control.vhd \
../../../hardware/system/data_channel_control.vhd \
../../../hardware/system/data_sink_mux.vhd \
../../../hardware/system/data_source_mux.vhd \
../../../hardware/system/fifo.vhd \
../../../hardware/system/data_channel.vhd \
../../../hardware/system/cordic_pkg.vhd \
../../../hardware/system/cordic.vhd \
../../../hardware/system/fixed_sine.vhd \
../../../hardware/system/float_sine.vhd \
../../../hardware/signal_processing/sine.vhd \
../../../hardware/system/task_sine.vhd \
../test_utility.vhd \
../test_avalon_slave.vhd \
../test_hardware_task.vhd \
../test_data_channel.vhd \
../../data/sine.vhd \
test_task_sine.vhd \
main = test_task_sine
expected_data = ../../data/sine.py
include ../data_tests.mk
tests/hardware/task_sine/test_task_sine.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
use work.test_utility.all;
use work.test_avalon_slave.all;
use work.task.all;
use work.sine_data.all;
use work.test_hardware_task.all;
use work.test_data_channel_pkg.all;
library std;
use std.env.all;
use std.textio.all;
entity test_task_sine is
generic( CHECK_RESULTS : boolean; GUI_MODE : boolean := false );
end entity test_task_sine;
architecture test of test_task_sine is
procedure test_configure( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable index : integer := 0;
variable writedata : std_logic_vector( 31 downto 0 );
begin
std.textio.write( std.textio.OUTPUT, " test_configure ... " );
index := 0;
writedata := x"08000000"; -- 2^32 / 32
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 1;
writedata := x"00000000";
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
index := 2;
writedata := x"40800000"; -- 2 ** 2 = 4 float
write_and_assert_config_eq( clk => clk, req => req, rsp => rsp,
index => index, config => writedata );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_configure;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal req : work.avalon_slave.Request;
signal rsp : work.avalon_slave.Response;
signal data_channel_req : work.avalon_slave.Request;
signal data_channel_rsp : work.avalon_slave.Response;
signal signal_write : std_logic;
signal signal_writedata : std_logic_vector( 31 downto 0 );
signal data_channel_read : std_logic;
signal data_channel_readdata : std_logic_vector( 31 downto 0 );
begin
dut : entity work.task_sine
port map (
clk => clk,
reset => reset,
address => req.address,
read => req.read,
readdata => rsp.readdata,
write => req.write,
writedata => req.writedata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
u_data_channel : entity work.data_channel
port map (
clk => clk,
reset => reset,
ctrl_address => data_channel_req.address,
ctrl_read => data_channel_req.read,
ctrl_readdata => data_channel_rsp.readdata,
ctrl_write => data_channel_req.write,
ctrl_writedata => data_channel_req.writedata,
hw_sink_write => signal_write,
hw_sink_writedata => signal_writedata,
hw_source_read => data_channel_read,
hw_source_readdata => data_channel_readdata
);
clk <= not clk after 10 ns;
reset_release : process
begin
wait for 35 ns;
reset <= '0';
wait;
end process reset_release;
stimulus : process
variable data_channel_config : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( reset );
work.test_data_channel_pkg.write_and_assert_config( clk => clk,
req => data_channel_req,
rsp => data_channel_rsp,
config => data_channel_config );
test_configure( clk => clk, req => req, rsp => rsp );
test_execute( clk => clk, req => req, rsp => rsp,
write => signal_write, writedata => signal_writedata );
if ( CHECK_RESULTS ) then
check_and_write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp,
expected => work.sine_data.expected );
else
write_content( clk => clk,
req => data_channel_req, rsp => data_channel_rsp );
end if;
if ( GUI_MODE ) then
std.env.stop;
else
std.env.finish;
end if;
end process stimulus;
end architecture test;
tests/hardware/task_sine/test_task_sine.wave
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$ version 1.1
/test_task_sine/*
/test_task_sine/dut/*
/test_task_sine/dut/u_sine/*
/test_task_sine/dut/u_sine/u_float_sine/*
/test_task_sine/dut/u_sine/u_float_sine/u_fixed_sine/*
/test_task_sine/u_data_channel/**
tests/hardware/task_sine/vsim.wave
+24
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /test_task_sine/*
add wave -noupdate /test_task_sine/dut/*
add wave -noupdate /test_task_sine/dut/u_sine/*
add wave -noupdate /test_task_sine/dut/u_sine/u_float_sine/*
add wave -noupdate /test_task_sine/dut/u_sine/u_float_sine/u_fixed_sine/*
add wave -noupdate /test_task_sine/u_data_channel/**
TreeUpdate [SetDefaultTree]
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
tests/hardware/test_avalon_slave.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
package test_avalon_slave is
procedure read( signal clk : in std_logic;
variable address : in std_logic_vector;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable data : out std_logic_vector );
procedure assert_readdata_eq( signal clk : in std_logic;
variable address : in std_logic_vector;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable expected : in std_logic_vector;
constant message : in string );
procedure write( signal clk : in std_logic;
variable address : in std_logic_vector;
signal req : out work.avalon_slave.Request;
variable data : in std_logic_vector );
end package test_avalon_slave;
package body test_avalon_slave is
procedure read( signal clk : in std_logic;
variable address : in std_logic_vector;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable data : out std_logic_vector ) is
begin
req.read <= '1';
req.write <= '0';
req.address <= address;
wait until falling_edge( clk );
wait until falling_edge( clk );
req.read <= '0';
data := rsp.readdata;
wait until falling_edge( clk );
end procedure read;
procedure assert_readdata_eq( signal clk : in std_logic;
variable address : in std_logic_vector;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable expected :in std_logic_vector;
constant message : in string ) is
variable readdata : std_logic_vector( expected'range );
begin
read( clk => clk,
address => address,
req => req,
rsp => rsp,
data => readdata );
assert( readdata = expected )
report message & LF &
" expected: " & to_string( expected ) & LF &
" actual: " & to_string( readdata ) & LF
severity error;
end procedure assert_readdata_eq;
procedure write( signal clk : in std_logic;
variable address : in std_logic_vector;
signal req : out work.avalon_slave.Request;
variable data : in std_logic_vector ) is
begin
req.read <= '0';
req.write <= '1';
req.address <= address;
req.writedata <= data;
wait until falling_edge( clk );
req.write <= '0';
end procedure write;
end package body test_avalon_slave;
tests/hardware/test_data_channel.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library work;
use work.avalon_slave.all;
use work.test_utility.all;
library std;
use std.textio.all;
package test_data_channel_pkg is
procedure is_empty( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable res : out boolean );
procedure assert_empty( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response );
procedure assert_not_empty( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response );
procedure assert_full( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response );
procedure assert_not_full( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response );
procedure assert_level( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable level : in std_logic_vector );
procedure assert_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable config : in std_logic_vector );
procedure write_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
variable config : in std_logic_vector );
procedure write_and_assert_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable config : in std_logic_vector );
procedure write_clear( signal clk : in std_logic;
signal req : out work.avalon_slave.Request );
procedure write_sw_sink( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
variable data : in std_logic_vector );
procedure read_sw_source( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable data : out std_logic_vector );
procedure assert_read_sw_source_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable expected : in std_logic_vector );
procedure write_hw_sink( signal clk : in std_logic;
signal write : out std_logic;
signal writedata : out std_logic_vector;
variable data : in std_logic_vector );
procedure assert_read_hw_source_eq( signal clk : in std_logic;
signal read : out std_logic;
signal readdata : in std_logic_vector;
variable expected : in std_logic_vector );
procedure write_content( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response );
procedure check_and_write_content( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
constant expected : real_array );
end package test_data_channel_pkg;
package body test_data_channel_pkg is
procedure is_empty( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable res : out boolean ) is
variable address : std_logic_vector( 3 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
constant EMPTY : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 1, address'length ) );
work.test_avalon_slave.read( clk => clk,
address => address,
req => req,
rsp => rsp,
data => data );
res := data = EMPTY;
end procedure is_empty;
procedure assert_empty( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable address : std_logic_vector( 3 downto 0 );
variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 1, address'length ) );
expected_readdata := x"00000001";
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => expected_readdata,
message => TEST_FAIL & " assert_empty" );
end procedure assert_empty;
procedure assert_not_empty( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable address : std_logic_vector( 3 downto 0 );
variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 1, address'length ) );
expected_readdata := x"00000000";
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => expected_readdata,
message => TEST_FAIL & " assert_not_empty" );
end procedure assert_not_empty;
procedure assert_full( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable address : std_logic_vector( 3 downto 0 );
variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 2, address'length ) );
expected_readdata := x"00000001";
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => expected_readdata,
message => TEST_FAIL & " assert_full" );
end procedure assert_full;
procedure assert_not_full( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable address : std_logic_vector( 3 downto 0 );
variable expected_readdata : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 2, address'length ) );
expected_readdata := x"00000000";
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => expected_readdata,
message => TEST_FAIL & " assert_not_full" );
end procedure assert_not_full;
procedure assert_level( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable level : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 3, address'length ) );
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => level,
message => TEST_FAIL & " assert_level" );
end procedure assert_level;
procedure assert_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable config : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 0, address'length ) );
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => config,
message => TEST_FAIL & " assert_config" );
end procedure assert_config;
procedure write_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
variable config : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 0, address'length ) );
work.test_avalon_slave.write( clk => clk,
address => address,
req => req,
data => config );
end procedure write_config;
procedure write_and_assert_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable config : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
write_config( clk => clk, req => req, config => config );
assert_config( clk => clk, req => req, rsp => rsp, config => config );
end procedure write_and_assert_config;
procedure write_clear( signal clk : in std_logic;
signal req : out work.avalon_slave.Request ) is
variable address : std_logic_vector( 3 downto 0 );
variable clear : std_logic_vector( 31 downto 0 ) := x"00000001";
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 6, address'length ) );
work.test_avalon_slave.write( clk => clk,
address => address,
req => req,
data => clear );
end procedure write_clear;
procedure write_sw_sink( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
variable data : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 4, address'length ) );
work.test_avalon_slave.write( clk => clk,
address => address,
req => req,
data => data );
end procedure write_sw_sink;
procedure read_sw_source( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable data : out std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 5, address'length ) );
work.test_avalon_slave.read( clk => clk,
address => address,
req => req,
rsp => rsp,
data => data );
end procedure read_sw_source;
procedure assert_read_sw_source_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable expected : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 5, address'length ) );
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => expected,
message => TEST_FAIL & " assert_readdata_eq" );
end procedure assert_read_sw_source_eq;
procedure write_hw_sink( signal clk : in std_logic;
signal write : out std_logic;
signal writedata : out std_logic_vector;
variable data : in std_logic_vector ) is
begin
wait until falling_edge( clk );
write <= '1';
writedata <= data;
wait until falling_edge( clk );
write <= '0';
end procedure write_hw_sink;
procedure assert_read_hw_source_eq( signal clk : in std_logic;
signal read : out std_logic;
signal readdata : in std_logic_vector;
variable expected : in std_logic_vector ) is
begin
wait until falling_edge( clk );
assert( readdata = expected )
report TEST_FAIL & " assert_read_hw_source_eq" & LF &
" expected: " & to_string( expected ) & LF &
" actual: " & to_string( readdata ) & LF
severity error;
wait until falling_edge( clk );
read <= '1';
wait until falling_edge( clk );
read <= '0';
end procedure assert_read_hw_source_eq;
procedure write_content( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response ) is
variable index : integer := 0;
variable empty : boolean;
variable value : std_logic_vector( 31 downto 0 );
variable float_value : float32;
variable real_value : real;
file data_file : text;
begin
std.textio.write( std.textio.OUTPUT, " write_content ... " );
file_open( data_file, "data.py", write_mode );
std.textio.write( data_file, "float_data = [" );
while true loop
is_empty( clk => clk, req => req, rsp => rsp, res => empty );
if ( empty ) then
exit;
end if;
read_sw_source( clk => clk, req => req, rsp => rsp,
data => value );
float_value := to_float( value );
real_value := to_real( float_value );
std.textio.write( data_file, to_string( real_value ) & "," );
index := index + 1;
end loop;
while index < 1024 loop
std.textio.write( data_file, "0.0 ," );
index := index + 1;
end loop;
std.textio.write( data_file, "]" & LF );
file_close( data_file );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure write_content;
procedure check_and_write_content( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
constant expected : real_array ) is
variable expected_readdata : std_logic_vector( 31 downto 0 );
variable index : integer := 0;
variable empty : boolean;
variable value : std_logic_vector( 31 downto 0 );
variable float_value : float32;
variable real_value : real;
variable expected_value : real;
variable abs_err : real := 0.5e-1;
file data_file : text;
begin
std.textio.write( std.textio.OUTPUT, " check_and_write_content ... " );
assert_full( clk => clk, req => req, rsp => rsp );
expected_readdata := std_logic_vector( to_unsigned( 0, expected_readdata'length ) );
assert_level( clk => clk, req => req, rsp => rsp,
level => expected_readdata );
file_open( data_file, "data.py", write_mode );
std.textio.write( data_file, "float_data = [" );
while true loop
is_empty( clk => clk, req => req, rsp => rsp, res => empty );
if ( empty ) then
exit;
end if;
read_sw_source( clk => clk, req => req, rsp => rsp,
data => value );
float_value := to_float( value );
real_value := to_real( float_value );
std.textio.write( data_file, to_string( real_value ) & "," );
expected_value := expected( index );
assert_element_near( real_value, expected_value, abs_err, index );
index := index + 1;
end loop;
std.textio.write( data_file, "]" & LF );
file_close( data_file );
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure check_and_write_content;
end package body test_data_channel_pkg;
tests/hardware/test_hardware_task.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg32.all;
use work.avalon_slave.all;
use work.test_utility.all;
use work.test_avalon_slave.all;
use work.task.all;
package test_hardware_task is
procedure read_state( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable state : out std_logic_vector );
procedure assert_state_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable state : std_logic_vector );
procedure assert_cycle_count_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable cycle_count : std_logic_vector );
procedure write_start( signal clk : in std_logic;
signal req : out work.avalon_slave.Request );
procedure write_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
variable index : in integer;
variable config : in std_logic_vector );
procedure assert_config_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable index : in integer;
variable config : in std_logic_vector );
procedure write_and_assert_config_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable index : in integer;
variable config : in std_logic_vector );
procedure assert_output_steam_data_eq( signal clk : in std_logic;
signal write : std_logic;
signal writedata : std_logic_vector;
signal expected : work.reg32.RegArray );
procedure test_execute( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
signal write : in std_logic;
signal writedata : in std_logic_vector );
end package test_hardware_task;
package body test_hardware_task is
procedure read_state( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable state : out std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 1, address'length ) );
work.test_avalon_slave.read( clk => clk,
address => address,
req => req,
rsp => rsp,
data => state );
end procedure read_state;
procedure assert_state_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable state : std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 1, address'length ) );
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => state,
message => TEST_FAIL & " assert_state_eq" );
end procedure assert_state_eq;
procedure assert_cycle_count_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable cycle_count : std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 2, address'length ) );
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => cycle_count,
message => TEST_FAIL & " assert_cycle_count_eq" );
end procedure assert_cycle_count_eq;
procedure write_start( signal clk : in std_logic;
signal req : out work.avalon_slave.Request ) is
variable address : std_logic_vector( 3 downto 0 );
variable start : std_logic_vector( 31 downto 0 ) := ( others => '0' );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 0, address'length ) );
work.test_avalon_slave.write( clk => clk,
address => address,
req => req,
data => START );
end procedure write_start;
procedure write_config( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
variable index : in integer;
variable config : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 3 + index, address'length ) );
work.test_avalon_slave.write( clk => clk,
address => address,
req => req,
data => config );
end procedure write_config;
procedure assert_config_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable index : in integer;
variable config : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
wait until falling_edge( clk );
address := std_logic_vector( to_unsigned( 3 + index, address'length ) );
work.test_avalon_slave.assert_readdata_eq( clk => clk,
address => address,
req => req,
rsp => rsp,
expected => config,
message => TEST_FAIL & " assert_config_eq" );
end procedure assert_config_eq;
procedure write_and_assert_config_eq( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
variable index : in integer;
variable config : in std_logic_vector ) is
variable address : std_logic_vector( 3 downto 0 );
begin
write_config( clk => clk, req => req, index => index, config => config );
assert_config_eq( clk => clk, req => req, rsp => rsp, index => index, config => config );
end procedure write_and_assert_config_eq;
procedure assert_output_steam_data_eq( signal clk : in std_logic;
signal write : std_logic;
signal writedata : std_logic_vector;
signal expected : work.reg32.RegArray ) is
begin
end procedure assert_output_steam_data_eq;
procedure test_execute( signal clk : in std_logic;
signal req : out work.avalon_slave.Request;
signal rsp : in work.avalon_slave.Response;
signal write : in std_logic;
signal writedata : in std_logic_vector ) is
variable expected_readdata : std_logic_vector( 31 downto 0 );
variable state : std_logic_vector( 31 downto 0 );
variable index : integer := 0;
begin
std.textio.write( std.textio.OUTPUT, " test_execute ... " );
expected_readdata := to_std_logic_vector( TASK_IDLE, expected_readdata'length );
assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );
write_start( clk => clk, req => req );
expected_readdata := to_std_logic_vector( TASK_RUNNING, expected_readdata'length );
assert_state_eq( clk => clk, req => req, rsp => rsp, state => expected_readdata );
while true loop
work.test_hardware_task.read_state( clk => clk, req => req, rsp => rsp, state => state );
if ( state = to_std_logic_vector( TASK_DONE, expected_readdata'length ) ) then
exit;
end if;
end loop;
std.textio.write( std.textio.OUTPUT, TEST_OK );
end procedure test_execute;
end package body test_hardware_task;
tests/hardware/test_utility.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
library std;
use std.textio.all;
package test_utility is
constant TEST_FAIL : string := "[ FAIL ]";
constant TEST_OK : string := "[ OK ]" & LF;
type real_array is array ( natural range <> ) of real;
procedure assert_eq( variable a : in std_logic_vector; variable b : in std_logic_vector );
procedure assert_near( variable a : in real;
variable b : in real;
variable abs_err : in real );
procedure assert_element_near( variable a : in real;
variable b : in real;
variable abs_err : in real;
variable index : in integer );
end package test_utility;
package body test_utility is
procedure assert_eq( variable a : in std_logic_vector; variable b : in std_logic_vector ) is
begin
assert( a = b )
report TEST_FAIL & "assert_eq" & LF &
" a: " & to_string( a ) & LF &
" b: " & to_string( b ) & LF
severity error;
end procedure assert_eq;
procedure assert_near( variable a : in real;
variable b : in real;
variable abs_err : in real ) is
variable abs_diff : real;
begin
abs_diff := abs( a - b );
assert( abs_diff <= abs_err )
report TEST_FAIL & "assert_near" & LF &
" a: " & to_string( a ) & LF &
" b: " & to_string( b ) & LF &
" " & to_string( abs_diff ) & " > " & to_string( abs_err ) & LF
severity error;
end procedure assert_near;
procedure assert_element_near( variable a : in real;
variable b : in real;
variable abs_err : in real;
variable index : in integer ) is
variable abs_diff : real;
begin
abs_diff := abs( a - b );
assert( abs_diff <= abs_err )
report TEST_FAIL & "assert_element_near" & LF &
" element: " & integer'image( index ) & LF &
" a: " & to_string( a ) & LF &
" b: " & to_string( b ) & LF &
" " & to_string( abs_diff ) & " > " & to_string( abs_err ) & LF
severity error;
end procedure assert_element_near;
end package body test_utility;
tests/hardware/vhdl.mk
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ghdl_version = $(shell ghdl --version 2> /dev/null)
vsim_version = $(shell vsim -version 2> /dev/null)
# in case verilog is part of the build a verilog capable simulator is required
ifdef verilog_srcs
ifneq (${vsim_version},)
include ../questa-sim.mk
else
$(error No HDL simulation tool found for verilog!)
endif
else
ifneq (${vsim_version},)
include ../questa-sim.mk
else
ifneq (${ghdl_version},)
include ../ghdl.mk
else
$(error No HDL simulation tool found!)
endif
endif
endif