Initial commit
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verilog_srcs = \
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../../../hardware/system/Butterfly.v \
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../../../hardware/system/DelayBuffer.v \
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../../../hardware/system/FFT1024_32B.v \
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../../../hardware/system/Multiply.v \
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../../../hardware/system/SdfUnit2.v \
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../../../hardware/system/SdfUnit.v \
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../../../hardware/system/Twiddle1024_32B.v \
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vhdl_srcs = \
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../../../hardware/system/reg32.vhd \
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../../../hardware/system/avalon_slave.vhd \
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../../hardware/test_data_channel.vhd \
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../../../hardware/system/avalon_slave_transitions.vhd \
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../../../hardware/system/task.vhd \
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../../../hardware/system/hardware_task_control.vhd \
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../../../hardware/system/hardware_task.vhd \
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../../../hardware/system/float.vhd \
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../../../hardware/system/squareRoot_pipe.vhd \
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../../../hardware/system/fft_magnitude_calc.vhd \
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../../../hardware/signal_processing/fft.vhd \
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../../../hardware/system/task_fft.vhd \
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../test_utility.vhd \
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../test_avalon_slave.vhd \
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../test_hardware_task.vhd \
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../../data/add_rand.vhd \
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../../data/sine.vhd \
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../../data/fft.vhd \
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test_task_fft.vhd \
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main = test_task_fft
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expected_data = ../../data/fft.py
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include ../data_tests.mk
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$ version 1.1
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/test_task_add_sine_cosine/*
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/test_task_add_sine_cosine/dut/*
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/test_task_add_sine_cosine/dut/u_add/*
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/test_task_add_sine_cosine/dut/u_add/u_float_add/*
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add wave -position end sim:/test_task_fft/dut/*
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