Studentenversion des ESY6/A Praktikums "signal_processing".
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crc.vhd 5.3KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library work;
  5. use work.reg32.all;
  6. use work.task.all;
  7. entity crc is
  8. port (
  9. clk : in std_logic;
  10. reset : in std_logic;
  11. task_start : in std_logic;
  12. task_state : out work.task.State;
  13. signal_read : out std_logic;
  14. signal_readdata : in std_logic_vector( 31 downto 0 );
  15. signal_write : out std_logic;
  16. signal_writedata : out std_logic_vector( 31 downto 0 )
  17. );
  18. end entity crc;
  19. architecture rtl of crc is
  20. signal current_task_state : work.task.State;
  21. signal next_task_state : work.task.State;
  22. signal index : integer range 0 to work.task.STREAM_LEN;
  23. --Selbst angelegte Signale
  24. signal data_valid_flag : std_logic;
  25. signal busy_flag : std_logic;
  26. signal result_valid_flag : std_logic;
  27. signal crc_vorher : signed( 31 downto 0);
  28. signal crc_nachher : signed( 31 downto 0 );
  29. signal komplett_ergebnis : signed( 31 downto 0 ); --Ergebnis muss zum Schluss evtl invertiert werden (siehe Software)
  30. signal wort : signed( 31 downto 0 );
  31. signal byte : signed( 7 downto 0 );
  32. --Zustände für die Zustandsmaschine für die Berechnung
  33. type CalcState is (
  34. CALC_IDLE,
  35. CALC_START,
  36. CALC_CRC,
  37. CALC_STORE_RESULT
  38. );
  39. --Signale für die Zustandsmaschine für die Berechnung
  40. signal current_calc_state : CalcState;
  41. signal next_calc_state : CalcState;
  42. -- Anmerkung zu CRC-Polynom:
  43. -- in Software wurde 0xEDB88320 CRC-32 Polynom (Invers) verwendet
  44. -- nicht invers waere 0x04C11DB7
  45. begin
  46. -- Eigener Core verwendet 0xEDB88320 als Polynom
  47. u_crc_core : entity work.crc_core -- Das hier ist der Core
  48. port map (
  49. crcIn => , --in std_logic_vector(31 downto 0)
  50. data => , --in std_logic_vector(7 downto 0);
  51. crcOut => --out std_logic_vector(31 downto 0)
  52. );
  53. -- Diesen Prozess nicht aendern
  54. task_state_transitions : process ( current_task_state, task_start, index ) is
  55. begin
  56. next_task_state <= current_task_state;
  57. case current_task_state is
  58. when work.task.TASK_IDLE =>
  59. if ( task_start = '1' ) then
  60. next_task_state <= work.task.TASK_RUNNING;
  61. end if;
  62. when work.task.TASK_RUNNING =>
  63. if ( index = work.task.STREAM_LEN - 1 ) then
  64. next_task_state <= work.task.TASK_DONE;
  65. end if;
  66. when work.task.TASK_DONE =>
  67. if ( task_start = '1' ) then
  68. next_task_state <= work.task.TASK_RUNNING;
  69. end if;
  70. end case;
  71. end process task_state_transitions;
  72. --Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Nur aus sine.vhd kopiert!
  73. calc_state_transitions: process (all) is
  74. begin
  75. next_calc_state <= current_calc_state;
  76. case current_calc_state is
  77. when CALC_IDLE=>
  78. if (current_task_state= work.task.TASK_RUNNING) then
  79. next_calc_state <= CALC_START;
  80. end if;
  81. when CALC_START=>
  82. next_calc_state <= CALC_CRC;
  83. when CALC_CRC =>
  84. if (result_valid_flag = '1' and busy_flag = '0') then --or falling_edge( busy) ?
  85. next_calc_state <= CALC_STORE_RESULT;
  86. end if;
  87. when CALC_STORE_RESULT =>
  88. if ( index = work.task.STREAM_LEN ) then
  89. next_calc_state <= CALC_IDLE;
  90. else
  91. next_calc_state <= CALC_START;
  92. end if;
  93. end case;
  94. end process calc_state_transitions;
  95. --Dieser Prozess war vorher schon drin, muss aber noch modifiziert werden
  96. sync : process ( clk, reset ) is
  97. begin
  98. if ( reset = '1' ) then
  99. current_task_state <= work.task.TASK_IDLE;
  100. index <= 0;
  101. elsif ( rising_edge( clk ) ) then
  102. current_task_state <= next_task_state;
  103. case next_task_state is
  104. when work.task.TASK_IDLE =>
  105. index <= 0;
  106. -- signal_write <= '0';
  107. when work.task.TASK_RUNNING =>
  108. index <= index + 1;
  109. --signal_write <= '1';
  110. --signal_writedata <= ( others => '0' );
  111. when work.task.TASK_DONE =>
  112. index <= 0;
  113. --signal_write <= '0';
  114. end case;
  115. end if;
  116. end process sync;
  117. crc_calc :process ( clk, reset ) is
  118. begin
  119. if ( reset = '1' ) then
  120. signal_read <= '0';
  121. signal_write <= '0';
  122. signal_writedata <= (others => '0');
  123. flag_index <= '0';
  124. elsif ( rising_edge( clk ) ) then
  125. case crc_state is --current oder next_calc_state
  126. when 0 =>
  127. signal_write <= '0';
  128. flag_index <= '0';
  129. if ( current_task_state = work.task.TASK_RUNNING ) then
  130. signal_read <= '1';
  131. crc_state <= 1; --Calc Zustand aendern. Sollte ueber Uebergangsschaltnetz geregelt werden
  132. end if;
  133. when 1 =>
  134. signal_read <= '0';
  135. --Berechne hier crc_out
  136. --Einfacher als Berechnung mit IP Core waere genau hier den ganzen Code davon reinkopieren
  137. crc_state <= 2; --Calc Zustand aendern
  138. when 2 =>
  139. if ( current_task_state = work.task.TASK_DONE ) then
  140. signal_writedata <= not(crc_out); --Ergebnis invertieren
  141. signal_write <= '1';
  142. end if;
  143. flag_index <= '1'; --flag_index sagt nur, dass der index hochgezaehlt werden soll
  144. crc_state <= 0; --Calc Zustand aendern
  145. -- assign new crc value
  146. crc_in <= crc_out;
  147. end case;
  148. end if;
  149. end process crc_calc;
  150. task_state <= current_task_state;
  151. end architecture rtl;