Versuch add abgeschlossen. Funktioniert auch praktisch!

hardware/signal_processing/add.vhd

@@ -72,7 +72,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN  ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -96,10 +96,10 @@ begin
 				if (done_flag = '1') then
 					next_calc_state <= CALC_STORE_RESULT;
 				end if;
-			when CALC STORE RESULT =>
+			when CALC_STORE_RESULT =>
 				next_calc_state <= CALC_IDLE;
 		end case;
-	end process calc state transitions;
+	end process calc_state_transitions;
 
 
 	--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks 
@@ -111,7 +111,7 @@ begin
 		elsif (rising_edge( clk)) then
 			current_task_state <= next_task_state; 
 			case next_task_state is
-				when work.task. TASK IDLE => null;
+				when work.task. TASK_IDLE => null;
 				when work.task. TASK_RUNNING => null; 
 				when work.task. TASK_DONE => null;
 			end case;
@@ -127,14 +127,17 @@ begin
 			ergebnis <= (others => '0'); 
 			ergebnis_valid <= '0';
 			signal_write <= '0';
-			signal_writedata <= (others => '0'); 
+			--signal_writedata <= (others => '0'); 
+			signal_a_read <= '0';
+			signal_b_read <= '0';
 		elsif (rising_edge( clk)) then
 			current_calc_state <= next_calc_state; 
 			ergebnis_valid <= '0';
 			case next_calc_state is 
 				when CALC_IDLE =>
 					start_flag <= '0';
-					signal_read <= '0';	--Daten wurden noch nicht verwendet.
+					signal_a_read <= '0';	--Daten wurden noch nicht verwendet.
+					signal_b_read <= '0';
 					signal_write <= '0';
 				when CALC_ADD => 				--hier Berechnung mit IP Core?
 					start_flag <= '1';
@@ -143,7 +146,9 @@ begin
 					index <= index + 1;
 					signal_write <= '1';
 					--signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core anschliessen
-					signal_read <= '1'	--mitteilen, dass die Daten gelesen wurden und jetzt neue Daten angelegt werden sollen
+					--mitteilen, dass die Daten gelesen wurden und jetzt neue Daten angelegt werden sollen
+					signal_a_read <= '1';	
+					signal_b_read <= '1';
 			end case;
 		end if;
 	end process sync;

tests/hardware/task_add_sine_cosine/data.py

@@ -0,0 +1 @@
+float_data = [2.000000e+00,2.779374e+00,3.526787e+00,4.213405e+00,4.812656e+00,5.301255e+00,5.660092e+00,5.874974e+00,5.937166e+00,5.843728e+00,5.597631e+00,5.207641e+00,4.687980e+00,4.057790e+00,3.340388e+00,2.562374e+00,1.752613e+00,9.411230e-01,1.579220e-01,-5.681200e-01,-1.210393e+00,-1.745568e+00,-2.154492e+00,-2.422919e+00,-2.542063e+00,-2.508927e+00,-2.326424e+00,-2.003255e+00,-1.553580e+00,-9.964671e-01,-3.551639e-01,3.438061e-01,1.071653e+00,1.798444e+00,2.494241e+00,3.130262e+00,3.679985e+00,4.120173e+00,4.431767e+00,4.600617e+00,4.618034e+00,4.481123e+00,4.192898e+00,3.762166e+00,3.203190e+00,2.535150e+00,1.781400e+00,9.685777e-01,1.255806e-01,-7.175397e-01,-1.530734e+00,-2.285103e+00,-2.954008e+00,-3.514094e+00,-3.946185e+00,-4.236010e+00,-4.374763e+00,-4.359427e+00,-4.192897e+00,-3.883861e+00,-3.446462e+00,-2.899757e+00,-2.266983e+00,-1.574657e+00,-8.515586e-01,-1.276198e-01,5.672265e-01,1.204198e+00,1.756773e+00,2.201711e+00,2.519947e+00,2.697327e+00,2.725152e+00,2.600517e+00,2.326424e+00,1.911666e+00,1.370490e+00,7.220590e-01,-1.029205e-02,-7.999488e-01,-1.618034e+00,-2.434522e+00,-3.219390e+00,-3.943765e+00,-4.581040e+00,-5.107891e+00,-5.505172e+00,-5.758650e+00,-5.859553e+00,-5.804902e+00,-5.597631e+00,-5.246466e+00,-4.765594e+00,-4.174114e+00,-3.495308e+00,-2.755738e+00,-1.984229e+00,-1.210763e+00,-4.653190e-01,2.232680e-01,8.284271e-01,1.326865e+00,1.699465e+00,1.932017e+00,2.015771e+00,1.947764e+00,1.730944e+00,1.374046e+00,8.912611e-01,3.016942e-01,-3.713790e-01,-1.101400e+00,-1.859553e+00,-2.615870e+00,-3.340388e+00,-4.004294e+00,-4.581041e+00,-5.047362e+00,-5.384174e+00,-5.577302e+00,-5.618034e+00,-5.503451e+00,-5.236544e+00,-4.826101e+00,-4.286365e+00,-3.636495e+00,-2.899828e+00,-2.102985e+00,-1.274848e+00,-4.454527e-01,3.551630e-01,1.098114e+00,1.756774e+00,2.307795e+00,2.732011e+00,3.015160e+00,3.148442e+00,3.128845e+00,2.959269e+00,2.648403e+00,2.210393e+00,1.664299e+00,1.033354e+00,3.440749e-01,-3.747627e-01,-1.093230e+00,-1.781400e+00,-2.410497e+00,-2.954008e+00,-3.388699e+00,-3.695518e+00,-3.860319e+00,-3.874419e+00,-3.734925e+00,-3.444852e+00,-3.013011e+00,-2.453666e+00,-1.785994e+00,-1.033354e+00,-2.223782e-01,6.180345e-01,1.457838e+00,2.266983e+00,3.016576e+00,3.679985e+00,4.233859e+00,4.659025e+00,4.941224e+00,5.071653e+00,5.047308e+00,4.871089e+00,4.551693e+00,4.103275e+00,3.544905e+00,2.899828e+00,2.194575e+00,1.457937e+00,7.198610e-01,1.029301e-02,-6.419711e-01,-1.210393e+00,-1.671717e+00,-2.006862e+00,-2.201657e+00,-2.247386e+00,-2.141128e+00,-1.885864e+00,-1.490370e+00,-9.688752e-01,-3.405190e-01,3.713790e-01,1.140226e+00,1.937166e+00,2.732194e+00,3.495309e+00,4.197658e+00,4.812656e+00,5.317002e+00,5.691571e+00,5.922154e+00,6.000000e+00,5.922154e+00,5.691571e+00,5.317003e+00,4.812656e+00,4.197658e+00,3.495308e+00,2.732194e+00,1.937166e+00,1.140226e+00,3.713790e-01,-3.405190e-01,-9.688742e-01,-1.490369e+00,-1.885864e+00,-2.141128e+00,-2.247387e+00,-2.201657e+00,-2.006862e+00,-1.671718e+00,-1.210394e+00,-6.419711e-01,1.029205e-02,7.198611e-01,1.457937e+00,2.194575e+00,2.899828e+00,3.544905e+00,4.103275e+00,4.551692e+00,4.871088e+00,5.047308e+00,5.071653e+00,4.941224e+00,4.659025e+00,4.233860e+00,3.679985e+00,3.016576e+00,2.266983e+00,1.457837e+00,6.180338e-01,-2.223787e-01,-1.033354e+00,-1.785995e+00,-2.453665e+00,-3.013009e+00,-3.444852e+00,-3.734925e+00,-3.874419e+00,-3.860320e+00,-3.695518e+00,-3.388701e+00,-2.954009e+00,-2.410497e+00,-1.781401e+00,-1.093230e+00,-3.747630e-01,3.440749e-01,1.033354e+00,1.664299e+00,2.210393e+00,2.648402e+00,2.959269e+00,3.128845e+00,3.148442e+00,3.015160e+00,2.732011e+00,2.307796e+00,1.756773e+00,1.098114e+00,3.551630e-01,-4.454528e-01,-1.274848e+00,-2.102985e+00,-2.899828e+00,-3.636494e+00,-4.286364e+00,-4.826100e+00,-5.236544e+00,-5.503451e+00,-5.618034e+00,-5.577302e+00,-5.384174e+00,-5.047363e+00,-4.581041e+00,-4.004294e+00,-3.340388e+00,-2.615870e+00,-1.859553e+00,-1.101400e+00,-3.713790e-01,3.016942e-01,8.912611e-01,1.374045e+00,1.730944e+00,1.947764e+00,2.015771e+00,1.932017e+00,1.699465e+00,1.326866e+00,8.284271e-01,2.232680e-01,-4.653190e-01,-1.210763e+00,-1.984229e+00,-2.755738e+00,-3.495308e+00,-4.174114e+00,-4.765593e+00,-5.246465e+00,-5.597631e+00,-5.804902e+00,-5.859553e+00,-5.758650e+00,-5.505172e+00,-5.107892e+00,-4.581042e+00,-3.943765e+00,-3.219390e+00,-2.434522e+00,-1.618034e+00,-7.999487e-01,-1.029205e-02,7.220590e-01,1.370490e+00,1.911664e+00,2.326424e+00,2.600517e+00,2.725152e+00,2.697327e+00,2.519947e+00,2.201712e+00,1.756774e+00,1.204198e+00,5.672265e-01,-1.276198e-01,-8.515589e-01,-1.574657e+00,-2.266983e+00,-2.899757e+00,-3.446461e+00,-3.883860e+00,-4.192897e+00,-4.359427e+00,-4.374762e+00,-4.236010e+00,-3.946184e+00,-3.514095e+00,-2.954009e+00,-2.285102e+00,-1.530734e+00,-7.175390e-01,1.255814e-01,9.685774e-01,1.781400e+00,2.535149e+00,3.203189e+00,3.762165e+00,4.192898e+00,4.481123e+00,4.618034e+00,4.600617e+00,4.431767e+00,4.120174e+00,3.679985e+00,3.130262e+00,2.494241e+00,1.798444e+00,1.071653e+00,3.4380Line truncated

tests/hardware/task_add_sine_cosine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 09:41:58 on Nov 20,2024
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.sine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.cosine_data
+# Loading work.sine_cosine_data
+# Loading work.test_task_add_sine_cosine(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.float_add(mixed)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_sine_cosine
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 09:41:59 on Nov 20,2024, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 1

tests/hardware/task_add_sine_cosine/work/@_opt2/VH_HASH_DATA

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+105 /users/ads1/brandlfl78731/linux/A_VHDL/signal_processing_vorlage/tests/hardware/task_add_sine_cosine/work
+2
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+9
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tests/hardware/task_add_sine_cosine/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology