Versuch 3 Hardware funktioniert Juhu!

hardware/signal_processing/crc.vhd

@@ -28,15 +28,18 @@ architecture rtl of crc is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	-- function berechne_crc(crc_in : signed( 31 downto 0 ), data : signed( 31 downto 0 )) return signed;
+
 	--Selbst angelegte Signale
 	signal data_valid_flag : std_logic;
 	signal busy_flag : std_logic;
 	signal result_valid_flag : std_logic;
-	signal crc_vorher : signed( 31 downto 0);
-	signal crc_nachher :  signed( 31 downto 0 );
-	signal komplett_ergebnis : signed( 31 downto 0 ); --Ergebnis muss zum Schluss evtl invertiert werden (siehe Software)
-	signal wort : signed( 31 downto 0 );
-	signal byte : signed(  7 downto 0 );
+
+	signal flag_index : bit := '0';
+	signal crc_state : integer range 0 to 2;
+
+	signal crcOut : std_logic_vector( 31 downto 0);
+	signal crcIn : std_logic_vector( 31 downto 0) := x"FFFFFFFF";
 
 	--Zustände für die Zustandsmaschine für die Berechnung
 	type CalcState is (
@@ -48,19 +51,13 @@ architecture rtl of crc is
 	--Signale für die Zustandsmaschine für die Berechnung
 	signal current_calc_state : CalcState;
 	signal next_calc_state : CalcState;
+	
 
 
 	-- Anmerkung zu CRC-Polynom:
 	-- in Software wurde 	0xEDB88320		CRC-32 Polynom (Invers) verwendet
 	-- nicht invers waere 	0x04C11DB7
 begin
-	-- Eigener Core verwendet 0xEDB88320 als Polynom
-	u_crc_core : entity work.crc_core					-- Das hier ist der Core
-	port map (
-		crcIn	=>	,	--in std_logic_vector(31 downto 0)
-		data	=>	,	--in std_logic_vector(7 downto 0);
-		crcOut	=>		--out std_logic_vector(31 downto 0)
-	);
 
 	-- Diesen Prozess nicht aendern
     task_state_transitions : process ( current_task_state, task_start, index ) is
@@ -119,7 +116,9 @@ begin
                 index <= 0;
                 -- signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                index <= index + 1;	
+				if ( flag_index = '1' ) then
+                	index <= index + 1;	
+				end if;
                 --signal_write <= '1';
                 --signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
@@ -148,19 +147,52 @@ begin
 			when 1 =>
 				signal_read <= '0';
 				--Berechne hier crc_out
+				--Die Berechnung muss für jedes Byte wieder durchgeführt werden
 				--Einfacher als Berechnung mit IP Core waere genau hier den ganzen Code davon reinkopieren
+				crcOut(0) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(16) xor crcIn(20) xor crcIn(22) xor crcIn(23) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(26);
+				crcOut(1) <= crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(17) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(27);
+				crcOut(2) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(18) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(28) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(28);
+				crcOut(3) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(19) xor crcIn(23) xor crcIn(25) xor crcIn(26) xor crcIn(29) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(29);
+				crcOut(4) <= crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(20) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(20) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(30);
+				crcOut(5) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(21) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(21) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(31);
+				crcOut(6) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(28) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(28) xor signal_readdata(29);
+				crcOut(7) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(8) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(9) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(31);
+				crcOut(10) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(13) xor crcIn(14) xor crcIn(18) xor crcIn(21) xor crcIn(22) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(26);
+				crcOut(11) <= crcIn(1) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(10) xor crcIn(14) xor crcIn(15) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(27);
+				crcOut(12) <= crcIn(2) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(11) xor crcIn(15) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28);
+				crcOut(13) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(12) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29);
+				crcOut(14) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(13) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(30);
+				crcOut(15) <= crcIn(1) xor crcIn(2) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(14) xor crcIn(18) xor crcIn(19) xor crcIn(23) xor crcIn(26) xor crcIn(27) xor crcIn(31) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(31);
+				crcOut(16) <= crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(15) xor crcIn(16) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28);
+				crcOut(17) <= crcIn(2) xor crcIn(5) xor crcIn(8) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(8) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29);
+				crcOut(18) <= crcIn(0) xor crcIn(3) xor crcIn(6) xor crcIn(9) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(19) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(18) xor crcIn(19) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(20) <= crcIn(0) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(17) xor crcIn(19) xor crcIn(22) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(21) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(12) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(12) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+				crcOut(22) <= crcIn(2) xor crcIn(7) xor crcIn(8) xor crcIn(13) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(13) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(23) <= crcIn(0) xor crcIn(3) xor crcIn(8) xor crcIn(9) xor crcIn(14) xor crcIn(19) xor crcIn(20) xor crcIn(21) xor crcIn(23) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(14) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(24) <= crcIn(2) xor crcIn(3) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(15) xor crcIn(16) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+				crcOut(25) <= crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(26) <= crcIn(2) xor crcIn(3) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(27) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(16) xor crcIn(19) xor crcIn(20) xor crcIn(23) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+				crcOut(28) <= crcIn(0) xor crcIn(4) xor crcIn(6) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
+				crcOut(29) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(7) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(30) <= crcIn(3) xor crcIn(4) xor crcIn(7) xor crcIn(14) xor crcIn(15) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
+				crcOut(31) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(15) xor crcIn(19) xor crcIn(21) xor crcIn(22) xor crcIn(25) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(31);
 
 				crc_state <= 2;		--Calc Zustand aendern
 			when 2 =>
 				if ( current_task_state = work.task.TASK_DONE ) then
-					signal_writedata <= not(crc_out);	--Ergebnis invertieren
+					signal_writedata <= not crcOut;	--Ergebnis invertieren
 					signal_write <= '1';
 				end if;		
 				
 				flag_index <= '1';	--flag_index sagt nur, dass der index hochgezaehlt werden soll
 				crc_state <= 0;		--Calc Zustand aendern
 				-- assign new crc value
- 				crc_in <= crc_out;
+ 				crcIn <= crcOut;
 
 			end case;
 		end if;

tests/hardware/task_crc/transcript

@@ -0,0 +1,62 @@
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# vsim -voptargs="+acc" work.test_task_crc -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gGUI_MODE=true -gCHECK_RESULTS=true 
+# Start time: 09:14:29 on Dec 18,2024
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Warning: (vopt-3040) Command line generic/parameter "GUI_MODE" not found in design.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "crc(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2.
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.crc_data
+# Loading work.fft_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.test_task_crc(test)#1
+# Loading work.task_crc(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.crc(rtl)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# do vsim.wave
+#  set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+#     test_execute ... [ OK ]
+#     test_crc_value ... [ OK ]
+# 1
+# Break in Process stimulus at test_task_crc.vhd line 131

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tests/hardware/task_crc/work/_vmake

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